US 5,091,339 A · Trenching techniques for forming vias and channels in multilayer electrical interconnects · patentgrep

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Abstract

Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.

Claims49

Dependent claims

A method for fabricating a multilayer electrical interconnect, comprising the following steps in the sequence set forth:

(a) providing an insulating layer on a base;
(b) forming a channel in the top surface and partially through the thickness of the insulating layer;
(c) forming a via in the top surface and completely through the thickness of the insulating layer adjacent the channel;
wherein forming the channel and via in steps (b) and (c) comprises:
covering the insulating layer with a hard mask having an opening to expose the channel and via, wherein the hard mask is non-erodible by an etch;
covering the hard mask with a soft mask having an opening to expose the via but covering the channel, wherein the soft mask is erodible by an etch;
applying an etch to remove material from the insulating layer where the via is exposed until the soft mask is completely eroded;
applying the etch after the soft mask is completely eroded to remove material from the insulating layer where the channel is exposed and material from the insulating layer remaining where the via is exposed until the channel and via are etched;
and then
removing the hard mask from the insulating layer, thereby forming the channel and via in the same step;
(d) depositing an electrical conductor into the channel and via;
and
(e) planarizing the interconnect top surface so that the electrically conductive layer remains only in the channel and via and is otherwise removed from the top surface of the insulating layer, and the interconnect top surface is substantially smooth, thereby forming an electrically conducting channel interconnected to an electrically conducting via.

10 more elements

A method for fabricating a multilayer electrical interconnect, comprising the following steps in the sequence set forth:

(a) providing an insulating layer on a base;
(b) forming a channel in the top surface and partially through the thickness of the insulating layer;
(c) forming a via in the top surface and completely through the thickness of the insulating layer adjacent the channel;
wherein forming the channel and via in steps (b) and (c) comprises:
covering the insulating layer with a lower soft mask having an opening to expose the channel and via, wherein the lower soft mask is erodible by an etch;
covering the lower soft mask with an upper soft mask having an opening to expose the via but covering the channel, wherein the upper soft mask is erodible by an etch;
applying an etch to remove material from the insulating layer where the via is exposed until the upper soft mask is either partially or completely eroded;
and
applying the etch after the upper soft mask is either partially or completely eroded to remove material from the insulating layer where the channel is exposed and material from the insulating layer remaining where the via is exposed until the lower soft mask is either partially or completely eroded and the channel and via are etched, thereby forming the channel and via in the same step;
(d) depositing an electrical conductor into the channel and via;
and
(e) planarizing the interconnect top surface so that the electrically conductive layer remains only in the channel and via and is otherwise removed from the top surface of the insulating layer, and the interconnect top surface is substantially smooth, thereby forming an electrically conducting channel interconnect to an electrically conducting via.

9 more elements

A method for fabricating a multilayer electrical interconnect, comprising the following steps in the sequence set forth:

(a) providing an insulating layer on a base;
(b) forming a channel in the top surface and partially through the thickness of the insulating layer;
(c) forming a via in the top surface and completely through the thickness of the insulating layer adjacent the channel;
wherein forming the channel and via in steps (b) and (c) comprises:
covering the insulating layer with a first soft mask having an opening to expose the via but covering the channel, wherein the first soft mask is erodible by a first etch;
applying a first etch to remove material from the insulating layer where the via is exposed and to either partially or completely erode the first soft mask;
covering the insulating layer with a second soft mask having an opening to expose the channel and via, wherein the second soft mask is erodible by a second etch;
and
applying a second etch to remove material from the insulating layer where the channel is exposed and material from the insulating layer remaining where the via is exposed until the second soft mask is either partially or completely eroded and the channel and via are etched, thereby forming the channel and via;
(d) depositing an electrical conductor into the channel and via;
and
(e) planarizing the interconnect top surface so that the electrically conductive layer remains only in the channel and via and is otherwise removed from the top surface of the insulating layer, and the interconnect top surface is substantially smooth, thereby forming an electrically conducting channel interconnect to an electrically conducting via.

9 more elements

A method for fabricating a multilayer electrical interconnect, comprising the following steps in the sequence set forth:

(a) providing an insulating layer on a base;
(b) forming a channel in the top surface and partially through the thickness of the insulating layer;
(c) forming a via in the top surface and completely through the thickness of the insulating layer adjacent the channel;
wherein forming the channel and via in steps (b) and (c) comprises:
covering the insulating layer with a first soft mask having an opening to expose the via and channel, wherein the first soft mask is erodible by a first etch;
applying a first etch to remove material from the insulating layer where the channel and via are exposed and to either partially or completely erode the first soft mask;
covering the insulating layer with a second soft mask having an opening to expose the via but covering the channel, wherein the second soft mask is erodible by a second etch;
and
applying a second etch to remove material from the insulating layer remaining where the via is exposed until the second soft mask is either partially or completely eroded and the channel and via are etched, thereby forming the channel and via;
(d) depositing a seed layer over the interconnect and into the channel and via, and then depositing an electrical conductor over the seed layer and into the channel and via wherein the deposited conductor substantially fills the channel and via;
and
(e) planarizing the interconnect top surface so that the electrically conductive layer remains only in the channel and via and is otherwise removed from the top surface of the insulating layer, and the interconnect top surface is substantially smooth, thereby forming an electrically conducting channel interconnected to an electrically conducting via.

9 more elements

A method for fabricating a multilayer electrical interconnect, comprising the following steps in the sequence set forth:

(a) providing an insulating layer on a base;
(b) forming a channel in the top surface and partially through the thickness of the insulating layer;
(c) forming a via in the top surface and completely through the thickness of the insulating layer adjacent the channel;
wherein forming the channel and via in steps (b) and (c) comprises:
stamping the insulating layer with a patterned plate comprising a channel abutment and a via abutment extending from a plate surface, so that the surface plate contacts the insulating layer, the channel abutment forms a channel indentation, and the via abutment forms a via indentation deeper than the channel indentation in the insulating layer;
retracting the plate from the insulating layer;
and
applying an etch to the interconnect to remove residual material from the insulating layer beneath the via indentation until the via is etched, thereby forming the channel and via in the same step;
(d) depositing an electrical conductor into the channel and via;
and
(e) planarizing the interconnect top surface so that the electrically conductive layer remains only in the channel and via and is otherwise removed from the top surface of the insulating layer, and the interconnect top surface is substantially smooth, thereby forming an electrically conducting channel interconnected to an electrically conducting via.

8 more elements

A method for fabricating a multilayer electrical interconnect, comprising the following steps in the sequence set forth:

(a) providing an insulating layer on a base;
(b) forming a channel in the top surface and partially through the thickness of the insulating layer;
(c) forming a via in the top surface and completely through the thickness of the insulating layer adjacent the channel;
wherein forming the channel and via in steps (a), (b) and (c) comprises the following steps in the sequence set forth:
providing a first photoimagible insulating layer having a thickness that defines the distance from the bottom of the channel to the base over the base;
providing a first mask which defines the via over the first photoimagible insulating layer;
directing a light source through the first mask at the first photoimagible insulating layer to alter the solubility of the exposed regions of the first photoimagible insulating layer;
removing regions of the first photoimagible insulating layer in the via;
providing a second photoimagible insulating layer with a thickness that defines the depth of the channel over the first photoimagible insulating layer;
providing a second mask which defines the channel and the via over the second photoimagible insulating layer;
directing a light source through the second mask at the second photoimagible insulating layer to alter the solubility of the exposed regions of the second photoimagible insulating layer;
and
removing material from the regions of the second photoimagible insulating layer in the channel and the via, thereby forming the channel and via;
(d) depositing an electrical conductor into the channel and via;
and
(e) planarizing the interconnect top surface so that the electrically conductive layer remains only in the channel and via and is otherwise removed from the top surface of the insulating layer, and the interconnect top surface is substantially smooth, thereby forming an electrically conducting channel interconnected to an electrically conducting via.

13 more elements

A method for fabricating a multilayer electrical interconnect, comprising the following steps in the sequence set forth:

(a) providing an insulating layer on a base;
(b) forming a channel in the top surface and partially through the thickness of the insulating layer;
(c) forming a via in the top surface and completely through the thickness of the insulating layer adjacent the channel;
wherein forming the channel and via in steps (b) and (c) comprises:
covering the insulating layer with a first soft mask having an opening to expose the via and channel, wherein the first soft mask is erodible by a first etch;
applying a first etch to remove material from the insulating layer where the channel and via are exposed and to either partially or completely erode the first soft mask;
covering the insulating layer with a second soft mask having an opening to expose the via but covering the channel, wherein the second soft mask is erodible by a second etch;
and
applying a second etch to remove material from the insulating layer remaining where the via is exposed until the second soft mask is either partially or completely eroded and the channel and via are etched, thereby forming the channel and via;
(d) depositing an electrical conductor into the channel and via by depositing a first electrical conductor into the via so that the first conductor fills the via substantially to the height of the bottom of the channel, depositing a seed layer over the interconnect and onto the first conductor and channel, and depositing a second electrical conductor over the seed layer so that the channel and via are substantially filled with the first and second conductors;
and
(e) planarizing the interconnect top surface so that the electrically conductive layer remains only in the channel and via and is otherwise removed from the top surface of the insulating layer, and the interconnect top surface is substantially smooth, thereby forming an electrically conducting channel interconnected to an electrically conducting via.

9 more elements

Dependencies are inferred from the claim text.