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US 5,086,500 AGranted
Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits
AssigneeTektronix, Inc.
InventorHans-Jurg Greub
Life of this patent
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Abstract
A reduced instruction set computer processor, having a rapid access, dual port register file for supplying operands to a high speed arithmetic logic unit, is implemented as a set of integrated circuits interconnected by constant impedance transmission lines and synchronized by a common clock signal. The transmission lines interconnecting the integrated circuits are formed by thin metallic foil conductors separated by dielectric polyimide membranes. The clock signal is adjustably delayed prior to transmission to each integrated circuit so that pulses of the clock signal arrive at each integrated circuit at the same time regardless of differences in inherent delays of the separate paths the clock signal must follow to each integrated circuit.
Claims13
A logic circuit comprising:
- a plurality of first integrated circuits, each containing circuitry carrying out operations synchronized to a clock signal;
- means for generating a master clock signal;
- a second integrated circuit comprising a plurality of delay circuits, each receiving said master clock signal as input and producing a separate output clock signal in delayed response to said master clock signal;
- and
- means for conveying the output clock signal produced by each delay circuit to a separate one of said first integrated circuits for synchronizing operations of circuitry contained therein,
- delays between said master clock signal and the output clock signals of the delay circuits being independently adjustable for compensating for delay differences in time of output clock signal arrival at said first integrated circuits.
3 more elements
A logic circuit comprising:
- a plurality of first integrated circuits, each for producing at least one output data signal and receiving at least one input data signal in synchronous relation to a clock signal;
- means for generating a master clock signal;
- a second integrated circuit comprising a plurality of delay circuits, each receiving said master clock signal as input and producing in response to said master clock signal a separate output clock signal in response to said master clock signal;
- and
- means for conveying ones of said input and output data signals between pairs of said first integrated circuits and for conveying the output clock signal produced by each delay circuit to a separate one of said first integrated circuits,
- delays between said master clock signal and the output clock signals of the delay circuits being independently adjustable for compensating for delay differences in time of output clock signal arrival at said first integrated circuits.
3 more elements
A computer processor comprising:
- a plurality of dielectric films;
- a plurality of conductor planes, each comprising at least one conductor, ones of said dielectric films being inserted between said conductor planes such that conductors of separate ones of said conductor planes form transmission lines for conveying signals, said transmission lines forming a first bus, a second bus, and a third bus;
- means for selectively transmitting data signals conveyed on said third busses to said first bus;
- a dual port addressable register file coupled to said first, second and third busses for receiving and storing data signals and for reading out stored data signals, said register file having a first port for receiving data signals conveyed on said first bus and for reading out data signals onto said second bus, and having a second port for receiving data signals conveyed on said third bus and for reading out data signals onto said third bus;
- arithmetic logic means for performing operations on data signals appearing on said second and third busses to produce output data signals said dual port addressable register file and said arithmetic logic means being implemented by a plurality of integrated circuits, each containing circuitry carrying out operations synchronized to a clock signal;
- and
- means for selectively placing said output data signals on said third bus.
4 more elements
A computer processor comprising:
- a plurality of dielectric films;
- a plurality of conductor planes, each comprising at least one conductor, ones of said dielectric films being inserted between said conductor planes such that conductors of separate ones of said conductor planes form transmission lines for conveying signals, said transmission lines forming a first bus, a second bus, and a third bus;
- at least one first integrated circuit comprising dual port addressable register means for storing data signals conveyed on said first and third busses, having a first port for receiving said first data signals conveyed on said first bus and for reading out stored data signals onto said second bus, and having a second port for receiving said third data signal conveyed on said third bus and for reading out stored data signals onto said third bus;
- and
- at least one second integrated circuit comprising arithmetic logic unit means for producing output data signals comprising programmably determined combinations of said second and third data signals, and means for selectively conveying said output data signals to said third bus.
2 more elements
A computer processor implemented as a plurality of integrated circuits, ones of said integrated circuits operating in timed relation to a pulsed clock signal transmitted thereto, said processor comprising:
- arithmetic logic means for producing an output data signal representing a combination of a plurality of input data signals;
- multiple port register file means for supplying said input data signals to said arithmetic logic unit means and for storing data conveyed by said output data signals, said multiple port register file means and said arithmetic logic unit means being implemented by separate ones of said integrated circuits;
- an integrated circuit comprising a plurality of delay circuits, each delay circuit receiving a pulsed master clock signal as input and producing a separate output clock signal in delayed response to said master clock signal;
- and
- signal transmission means comprising metallic conductors separated by dielectric films forming transmission lines for conveying said input data signals and said output data signals between data signals and said output data signals between said register file means and said arithmetic logic mans, and for conveying separate ones of said output clock signals as pulsed clock signal input to said separate ones of said integrated circuits,
- delays between said master clock signal and the output clock signals of the delay circuits being independently adjustable for compensating for delay differences in time of output clock signal arrival at said first integrated circuits.
3 more elements
Dependencies are inferred from the claim text.