Sense amplifier and method for ferroelectric memory

A ferroelectric random access memory, comprising:

• an array of ferroelectric memory cells arranged in rows and columns, each column of memory cells being coupled to a distinct bit line, each memory cell being selectively coupled to said corresponding bit line by an access control transistor so that only one memory cell in said column is coupled to said bit line at a time;
• at least one sense amplifier coupled to one of said bit lines, said sense amplifier including first and second sample and hold means for sampling and holding a voltage level on said bit line, and a differential amplifier which outputs a first bit value when the voltage level held in said first sample and hold means exceeds the voltage level held in said second sample and hold means by at least a predefined threshold and otherwise outputs a second bit value which is the inverse of said first bit value;
• and
• control means, coupled to said array of memory cells and said at least one sense amplifier, for strobing a selected memory cell a first time, storing a resulting data voltage level on the bit line coupled to said selected memory cell in said first sample and hold means of said sense amplifier, then strobing said selected memory cell a second time, storing a resulting reference voltage level on the bit line coupled to said selected memory cell in said second sample and hold means of said sense amplifier, and then enabling said differential amplifier so as to generate an output bit value.

A method of operating a ferroelectric random access memory, said memory containing an array of ferroelectric memory cells arranged in columns, each column of memory cells being coupled to a distinct bit line, each memory cell being selectively coupled to said corresponding bit line by an access control transistor so that only one memory cell in said column is coupled to said bit line at a time;

• the steps of the method comprising:
• selecting a memory cell in at least one of said columns of memory cells by enabling said memory cell's access control transistor and thereby coupling said selected memory cell to a bit line;
• strobing said selected memory cell so as to produce a data voltage level on said bit line indicative of data stored in said selected memory cell;
• sampling and holding said voltage level on said bit line in a first sample and hold circuit;
• strobing said selected memory cell a second time so as to produce a reference voltage level on said bit line indicative of device characteristics of said selected memory cell;
• sampling and holding said reference voltage level on said bit line in a second sample and hold circuit;
• comparing said data voltage level stored in said first sample and hold circuit with said reference voltage level stored in said second sample and hold circuit, and generating an output bit value based on said comparison.