Circuit arrangement for decimal arithmetic

A circuit for decimal arithmetic comprising:

• (a) a first register for storing a minuend in Binary Coded Decimal (BCD) representation,
• (b) a second register for storing a subtrahend in BCD representation,
• (c) a third register,
• (d) a carry status decision means for producing a first signal as a carry status when the subtrahend is larger than the minuend and a second signal as the carry status when the subtrahend is less than the minuend in a first subtraction,
• (e) a carry status register connected to the carry status decision means for holding the carry status sent from the carry status decision means,
• (f) a zero generation means for generating a zero in BCD representation;
• (g) a binary coded decimal subtraction means for receiving the minuend from the first register and the subtrahend from the second register, performing the first subtraction and after the first subtraction of the subtrahend from the minuend, storing a result of the first subtraction in the second register and in the third register, and subsequently storing the zero in the first register, and for subtracting the result of the first subtraction from the zero in the first register, and
• (h) an inhibition means for preventing the third register from storing the result of the second subtraction when the carry status register holds the second signal, the inhibition means further assigning a positive sign to the result in the third register if the preventing takes place and a negative sign to the result in the third register if no preventing occurs.