US 5,084,891 A · Technique for jointly performing bit synchronization and error detection in a TDM/TDMA system

Abstract

A technique for bit synchronization and error detection of received digital data bursts in a TDM/TDMA system, such as that which will be used with low power portable digital telephony. A cyclically redundant codeword, e.g. a (161,147) codeword, is formed for transmission, using e.g. either a TDM packet or TDMA burst. The first and last bits in the codeword are then inverted to form a first set of marker bits. At a receiver, a second set of marker bits is inserted into a received word, again through inverting the first and last bits. The resulting marked word is then rotated by a pre-determined number of bits to place potentially erroneous bits at the end of this word. A multi-bit timing syndrome value is then determined and is used to access a look-up table for a value of bit slippage. The received word is advanced or retarded as specified by the bit slippage value to yield an intermediate word. The marker bits are removed from the intermediate word to yield an unmarked word for which an error syndrome value is determined. If the error syndrome value is zero, then the unmarked word is a synchronized substantially error-free codeword. If the unmarked word contains excessive bit slippage or bit errors indicated by an excessive value of the timing syndrome or a non-zero valued error syndrome, an indication is provided to ignore this word.

Claims38

Dependent claims

A method for performing bit synchronization and error detection on a received word having first marker bits and for providing a synchronized substantially error-free cyclic codeword corresponding thereto to an output point comprising the steps of:

inserting second marker bits into said received word so as to form a marked received word;
determining, in response to said marked received word, a multi-bit timing syndrome value therefor and, in response thereto, a corresponding value of bit slippage associated therewith;
advancing or retarding the received word by an amount of bit positions and in a direction specified by said bit slippage value to yield an intermediate word;
removing the first marker bits from said intermediate word to yield an unmarked word;
determining, in response to said unmarked word, a multi-bit error syndrome value therefor;
and
testing said error syndrome value to determine whether no bit errors exist in said unmarked word and, in the event said bit errors do not exist providing said unmarked word as the synchronized substantially error-free codeword to the output point.

4 more elements

A method for transmitting an informational bit stream of digital data through a communication channel from a transmitter to a receiver and at said receiver for recovering bit synchronization and performing error detection of a corresponding received bit stream comprising the steps of:

at the transmitter:
determining a plurality of parity bits for the informational bit stream;
generating a first cyclic codeword formed of the informational bit stream and said parity bits;
inserting first marker bits in said first cyclic codeword so as to form a marked first cyclic codeword;
and
transmitting a first burst comprising said marked first cyclic codeword over said channel to said receiver;
and
at the receiver:
receiving a second burst corresponding to said transmitted first burst from said channel and extracting from said second burst a first word corresponding to said marked first cyclic codeword;
inserting second marker bits into said first word so as to form a marked received word;
determining, in response to said marked received word, a multi-bit timing syndrome value therefor and, in response thereto, a corresponding value of bit slippage associated therewith;
advancing or retarding the received word by an amount of bit positions and in a direction specified by said bit slippage value to yield an intermediate word;
removing the first marker bits from said intermediate, word to yield an unmarked word;
determining, in response to said unmarked word, a multi-bit error syndrome value therefor;
and
testing said error syndrome value to determine whether no bit errors exist in said unmarked word and, in the event, said bit errors do not exist, providing said unmarked word as a synchronized substantially error-free codeword to an output point.

13 more elements

Apparatus for performing bit synchronization and error detection on a received word having first marker bits and for providing a synchronized substantially error-free cyclic codeword corresponding thereto to an output point comprising:

means for inserting second marker bits into said received word so as to form a marked received word;
means for determining, in response to said marked received word, a multi-bit timing syndrome value therefor and, in response thereto, a corresponding value of bit slippage associated therewith;
means for advancing or retarding the received word by an amount of bit positions and in a direction specified by said bit slippage value to yield an intermediate word;
means for removing the first marker bits from said intermediate word to yield an unmarked word;
means for determining, in response to said unmarked word, a multi-bit error syndrome value therefor;
and
means for testing said error syndrome value to determine whether no bit errors exist in said unmarked word and, in the event said bit errors do not exist providing said unmarked word as the synchronized substantially error-free codeword to the output point.

4 more elements

Apparatus for transmitting an informational bit stream of digital data through a communication channel from a transmitter to a receiver and at said receiver for recovering bit synchronization and performing error detection of a corresponding received bit stream comprising:

means for determining a plurality of parity bits for the informational bit stream;
means for generating a first cyclic codeword formed of the informational bit stream and said parity bits;
means for inserting first marker bits in said first cyclic codeword so as to form a marked first cyclic codeword;
and
means for transmitting a first burst comprising said marked first cyclic codeword over said channel to said receiver;
means for receiving a second burst corresponding to said transmitted first burst from said channel and extracting from said second burst a first word corresponding to said marked first cyclic codeword;
means for inserting second marker bits into said first word so as to form a marked received word;
means for determining, in response to said marked received word, a multi-bit timing syndrome value therefor and, in response thereto, a corresponding value of bit slippage associated therewith;
means for advancing or retarding the received word by an amount of bit positions and in a direction specified by said bit slippage value to yield an intermediate word;
means for removing the first marker bits from said intermediate word to yield an unmarked word;
means for determining, in response to said unmarked word, a multi-bit error syndrome value therefor;
and
means for testing said error syndrome value to determine whether no bit errors exist in said unmarked word and, in the event, said bit errors do not exist, providing said unmarked word as a synchronized substantially error-free codeword to an output point.

10 more elements

Dependencies are inferred from the claim text.

Technique for jointly performing bit synchronization and error detection in a TDM/TDMA system

Life of this patent

Technique for jointly performing bit synchronization and error detection in a TDM/TDMA system

Life of this patent

Abstract

Claims38