Enhanced test circuit
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel, Jr.
Life of this patent
Estimating the term…
Abstract
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.
Claims21
A test circuit within an integrated circuit comprising:
- a test cell having an input for receiving data, an output for supplying data, an input for receiving test data, an output for supplying test data, and operable to selectively store one of said inputs to said cell;
- and
- compare circuitry within said test cell to compare said input for receiving data to a predefined value and generate a control signal indicative of whether said input matches said predefined value.
The test circuit within an integrated circuit comprising:
- a plurality of test cells each coupled to an input or output of the integrated circuit and having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, each having an output for transmitting test data to other test cells;
- and
- one or more of said test cells having signature analysis circuits operable to calculate a checksum on a stream of data input to the test circuit.
A test circuit within an integrated circuit comprising:
- a plurality of test cells operable to store respective inputs to a plurality thereto;
- said test cells also operable to input and output data for an integrated circuit and operable to input and output test data;
- and
- one or more of said test cells having pattern generation circuitry operable for generating a pseudo-random pattern, each having an input for received pattern generation data from other respective test cells and an output for transmitting pattern generation data to other respective test cells, associated ones of respective test cells operable to generate a programmable width pseudo-random pattern.
Test circuitry on-board an integrated circuit, comprising:
- input and output buffer circuitry for receiving and transmitting user defined data and control signals;
- and
- test circuits coupled to said input and output buffer circuitry made up of a plurality of test cells operable to store respective inputs to a plurality thereto;
- each of said test cells having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, and each having an output for transmitting test data to other test cells.
Test circuitry on-board an integrated circuit, comprising:
- input and output buffer circuitry operable to receive and transmit user defined data and control signals;
- test circuitry coupled to said input and output circuitry and comprised of a plurality of test cells operable to store respective inputs thereto;
- each of said test cells having an input for receiving data, each having an output for supplying data, each of the test cells operable to store data input to said test cell, and each having an output for transmitting test data to the other test cells;
- and
- one or more of said test cells having pattern generation circuitry operable for generating a pseudo-random pattern, having an input for receiving pattern generation data from other respective test cells and an output for transmitting pattern generation data to other respective test cells, associated ones of respective test cells operable to generate a programmable width pseudo-random pattern.
Dependencies are inferred from the claim text.