Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof

#This invention is in the field of integrated circuits, and is more specifically directed to on chip power supply buses.

#A problem VLSI circuit designers face is how to minimize noise in the on chip power supply buses. Many factors contribute to noise in the power supply buses. One such factor, for example, is the switching of high speed output buffer circuitry. As the speed of transition is increased by increasing the drive capability of the output buffer circuits, the parasitic inductance associated with the connection of the output buffer circuits to the power supply buses increases, thereby generating noise. Other contributing factors include chip size and refresh current. Larger chip sizes for increased memory capacity devices have longer on chip power supply buses and therefore have more inductance. In dynamic random access memory devices, DRAM's (as in 16 megabit DRAM's having 2.sup.24 memory cells), higher currents for refresh cycles result in higher voltage drops in the Vss and Vdd buses.

#Designers try to minimize noise in the on chip power supply buses in a variety of ways. Improved output buffer circuits switching at different times minimizes "dirty" voltage. Output buffer circuits near power supply bonding pads along the edge of the silicon die reduces the length of current travel. Short wire bonds connecting the power supply bonding pads to lead fingers of the lead frame further reduce inductance.

#FIG. 1 is a top view drawing illustrating a prior art integrated circuit device.

#FIG. 2 is a partial side view drawing of the end of I/C device 9 of FIG. 1 by bonding pad 11p.

#FIG. 3 is a side view drawing illustrating the preferred embodiment of the invention.

#FIG. 1 is a top view drawing illustrating a prior art integrated circuit device, it being well known to VLSI designers how to construct an I/C device having a semiconductor chip attached by wire bonds to a lead frame. Integrated circuit device 9 can be any MOS device, such as a gate array, or a DRAM, formed on semiconductor chip 10. The active devices, not shown, of semiconductor chip 10 are connected to respective bonding pads 11a-11p for external connection. In a DIP package, there are usually 16 such bonding pads 11 that are typically formed of aluminum. The bonding pads 11 usually lie along the edges of semiconductor chip 10. Wire bonds 12 connect lead fingers 13 to bonding pads 11. Wire bonds 12 are typically gold. A substance such as plastic typically encapsulates chip 10, wire bonds 12, and parts of lead fingers 13. I/C device 9 is typically mounted to a printed circuit board.

#FIG. 2 is a partial side view drawing of the end of I/C device 9 by bonding pad 11p. Semiconductor Chip 10 is formed of silicon layer 14, passivation oxide layer 16, and pix 17. The active circuits lie in silicon layer 14 as is well known in the art. Aluminum bonding pad 11p is illustrated lying on top of silicon layer 14. In construction, passivation oxide layer 16 is applied on top of silicon layer 14 and bonding pads 11. Pix 17 is applied over passivation oxide layer 16. The device is etched so that a via 18 is formed through pix 17 and passivation oxidation layer 16 to the surface of bonding pads 11. Semiconductor chip 10 is usually attached to a die attach 15 for connection to a lead frame. Wire bond 12p has one end connected to lead finger 13p. The other end of wire bond 12p passes through via 18p and is connected to the surface of bonding pad 11p. The dotted line in FIG. 2 illustrates the encapsulation material.

#Integrated circuit device 9 of FIGS. 1 and 2 receives externally provided power. The external power is received by connecting a lead finger to a power supply. Power is transferred from the power supply, through the lead finger, through the wire bond, through the bonding pad, and is distributed throughout the chip. Ground voltage Vss, and positive voltage Vdd, usually of +5.0 volts, are supplied through separate lead fingers. In FIG. 1, for example, Vss may be connected to lead finger 13a and Vdd may be connected to lead finger 13p.