Electronically variable delay line
AssigneeDigital Equipment Corporation
InventorsThomas B. Hawkins, Douglas A. MacIntyre, Johannes A. S. Bjorner
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Abstract
An electronically variable delay line having adjustable delay and bandwidth characteristics is provided. A varactor diode functioning as a variable controlled capacitance is coupled between a signal conductor and a ground reference conductor, thereby segmenting the signal conductor into two, individual smaller segments of conductor which function as fixed inductances. The delay characteristic of the line is adjusted by varying the varactor's biasing voltage which, in turn, varies the varactor's capacitance. A staggered termination technique is implemented to stabilize the insertion loss characteristics of the delay line.
Claims13
A variable delay line configured for propagating signals with an electronically adjustable delay characteristic comprising:
- a signal conductor;
- a ground reference conductor;
- a variable-capacitance varactor coupled between said ground conductor and said signal conductor;
- means for adjusting the capacitance of said varactor to thereby vary said delay characteristic of said delay line;
- and
- impedance optimizing resistive means coupled between said signal conductor and said ground conductor for terminating said delay line and minimizing multiple reflections of said signals over the range of said delay characteristic of said delay line,
- wherein said impedance optimizing resistive means includes an input resistance coupled across an input end of said delay line and an output resistance coupled across an output end of said delay line, and wherein said input resistance and said output resistance are substantially different.
A variable delay line having input and output ends, and having an electronically adjustable delay characteristic and a characteristic impedance that varies between a minimum impedance and a maximum impedance depending upon said adjusted delay characteristic, said variable delay line comprising:
- conducting path means for propagating signals between said input and said output ends of said delay line;
- variable reactance means coupled to said conducting path means for changing said delay characteristic of said delay line in response to a control signal applied to said reactance means;
- and
- a first resistance coupled to said conducting path means at said input end and a second resistance coupled to said conducting path means at said output end, said first resistance and said second resistance terminating said conducting path means to minimize multiple reflections of said signals propagating through said conducting path means,
- wherein said signals are largely absorbed at said input end or said output end after a single reflection when said characteristic impedance of said delay line is at said minimum impedance or said maximum impedance and wherein said signals are partly absorbed at each end so as to largely absorb them after two reflections when said characteristic impedance of said delay line varies between said minimum impedance and said maximum impedance.
A variable delay line having a first end and a second end and configured for propagating signals to circuitry having a nominal characteristic impedance value, said variable delay line also having an electronically adjustable delay characteristic and a characteristic impedance that varies between a minimum impedance value and a maximum impedance value depending upon said adjusted delay characteristic, said variable delay line comprising:
- a conducting path connected between said first end and said second end of said delay line;
- variable capacitive means coupled to said conducting path for changing said delay characteristic of said variable delay line in response to a control signal applied to said capacitive means;
- and
- a first resistance coupled to said conducting path at said first end and having a value greater than said nominal characteristic impedance value, and a second resistance coupled to said conducting path at said second end and having a value less than said nominal characteristic impedance value, said resistances terminating said variable delay line to minimize multiple reflections of said signals propagating through said delay line,
- wherein said signals are largely absorbed at said first end or said second end after a single reflection when said characteristic impedance of said delay line is at said minimum impedance value or said maximum impedance value and wherein said signals are partly absorbed at each end so as to largely absorb them after two reflections when said characterstic impedance of said delay line varies between said minimum impedance value and said maximum impedance value.
Dependencies are inferred from the claim text.