Method and apparatus for graphics display data manipulation

In a digital processor for generating display data for rendering a graphical representation of a three dimensional object on a display screen, said display screen comprising a plurality of pixels, an apparatus for selectively updating said pixels comprising:

• (a) first register means for storing a plurality of first Z-values, each such first Z-value corresponding to one of said pixels and representing a distance from a reference plane to a corresponding point of a first three-dimensional object rendered on said display screen;
• (b) second register means for storing a plurality of second Z-values, each such second Z-value corresponding to one of said pixels and representing a distance from said reference plane to a corresponding point of a second three-dimensional object to be rendered on said display screen;
• (c) comparator means for comparing N of said first Z-values with N corresponding second Z-values;
• (d) pixel mask means having at least N-bits, each bit for storing a result of a corresponding one of said comparisons between said first and second Z-values;
• (e) frame buffer means for storing a plurality of first pixel values representing said first object;
• (f) third register means for storing a plurality of second pixel values representing said second object;
• and
• (g) data path means for selectively storing in said frame buffer means corresponding ones of said second pixel values as a function of a corresponding bit of said pixel mask means.

In a digital processor for sequentially performing operations on a plurality of data words in synchronism with a clock signal, a method for selectively designating a data word to be updated comprising the steps of:

• (a) storing a plurality of first data words in a first memory means, said first data words representing respective first data values;
• (b) designating a register to store a mask comprising a plurality of bits, each such bit corresponding to one of said first data words;
• (c) for each of a designated subset of said first data words, computing and storing a corresponding updated first data value;
• (d) shifting said mask register by a predetermined number of bits N;
• (e) selecting N of said updated first data values;
• (f) comparing said N updated first data values with N corresponding first data words retrieved from said first memory means;
• and
• (g) setting a corresponding i.sup.th bit of said mask register if an i.sup.th one of said N updated first data values has a predetermined mathematical relationship to said corresponding first data word retrieved from said first memory means;
• wherein steps (d), (e), (f), and (g) are performed substantially concurrently during a single cycle of said clock signal.

In a digital processor for performing operations on a plurality of data words, an apparatus for selectively updating one of said data words comprising;

• (a) first memory means for storing a plurality of first data words representing first data values;
• (b) first register means for storing a plurality of updated first data values;
• (c) comparator means for comparing N of said first data words with N corresponding updated first data values;
• (d) mask means having at least N-bits, each bit for storing a result of a corresponding one of said comparisons between said first data words and said updated first data values;
• (e) second memory means for storing a plurality of second data words representing second data values, said second data words being logically associated with said first data words;
• (f) second register means for storing a plurality of updated second data values;
• and
• (g) data path means for selectively storing in said second memory means corresponding ones of said updated second data values as a function of a corresponding bit of said mask means.