Power efficient sustain drivers and address drivers for plasma panel

Addressing apparatus for addressing cells defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in an ac plasma panel, said addressing apparatus comprising:

• means for charging a plurality of address electrodes of one dimension array to a high level of one polarity;
• means for selective discharging of non-selected charged address electrodes of said plurality and maintaining the high level of one polarity at selected charged address electrodes in accordance with desired information to be entered into the plasma panel;
• and
• means for applying a high level of opposite polarity charge to a respective address electrode of the other dimension array after said selective discharging of non-selected charged address electrodes for discharging cells at said selected charged address electrodes and entering the desired information into the plasma panel.

A method of addressing address cells defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in an ac plasma panel, said method of addressing comprising the steps of:

• charging a plurality of address electrodes of one dimension array to a high level of one polarity;
• selective discharging of non-selected charged address electrodes of said plurality without discharging selected charged address electrodes of said plurality in accordance with desired information to be entered into the plasma panel;
• and
• applying a high level of opposite polarity charge to a respective address electrode of the other dimension array for discharging address cells associated with the selected charged address electrodes of said plurality and entering the desired information into the plasma panel.

Addressing apparatus for addressing pixels defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in a display panel, said addressing apparatus comprising:

• means for applying a high level pulse of one polarity to address electrodes of one dimension array;
• means for selective discharging of non-selected address electrodes without discharging selected address electrodes in accordance with desired information to be entered into the display panel;
• and
• means for applying a high level pulse of opposite polarity to a respective address electrode of the other dimension array after said selective discharging for entering the desired information into the display panel.

Addressing apparatus for addressing pixels defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in a display panel, said addressing apparatus comprising:

• means for charging address electrodes of one dimension array to a high level of one polarity;
• means for selective discharging of non-selected charged address electrodes without discharging selected charged address electrodes to maintain the high level of one polarity at said selected charged address electrodes in accordance with desired information to be entered into the display panel;
• and
• means for applying a high level of opposite polarity charge to a respective address electrode of the other dimension array after said selective discharging of non-selected charged address electrodes for entering the desired information into the display panel.

A method of addressing address cells defined by the intersection of respective address electrodes in respective arrays of X and Y dimension address electrodes in a display panel, said method of addressing comprising the steps of:

• charging address electrodes of one dimension array to a high level of one polarity;
• selective discharging non-selected but not selected charged address electrodes in accordance with desired information to be entered into the display panel;
• and
• applying a high level of opposite polarity charge to a respective address electrode of the other dimension array after said selective discharging for entering the desired information into the display panel.

A display panel comprising:

• an array of X dimension address electrodes;
• an intersecting array of Y dimension address electrodes, where intersections between respective X and Y address electrodes define respective display pixels;
• address means for applying an addressing signal during an addressing cycle to selected X and Y address electrodes to activate at least one display pixel;
• said address means including, means for charging more than one address electrode of said X or Y dimension array to a high level of one polarity;
• means for selective discharging non-selected but not selected charged address electrodes in accordance with desired information to be entered into the display panel;
• and
• means for applying a high level pulse of opposite polarity to a respective address electrode of the other said X or Y dimension array after said selective discharging for entering the desired information into the display panel.

An ac plasma panel comprising:

• an array of X dimension electrodes;
• an intersecting array of Y dimension electrodes with the intersections between respective X and Y electrodes defining a gas discharge cell;
• address means for applying a signal to selected X and Y electrodes to discharge at least one gas discharge cell;
• said address means including, means for charging more than one address electrode of said X or Y dimension array to a high level of one polarity;
• means for selective discharging nonselected but not selected charged address electrodes to maintain the high level of one polarity at said selected charged address electrodes in accordance with desired information to be entered into the plasma panel;
• and
• means for applying a high level pulse of opposite polarity to a respective address electrode of the other said X or Y dimension array after said selective discharging for discharging said one gas discharge cell and entering the desired information into the plasma panel.

A display panel having panel electrodes and panel capacitance, and an energy recovery sustain circuit coupled to the panel electrodes for driving said display panel, said energy recovery sustain circuit including;

• an inductor coupled to said panel electrodes for charging and discharging the panel capacitance;
• means for charging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero;
• first means for clamping the voltage level of said panel capacitance upon the inductor current reaching zero during charging of the panel capacitance;
• means for discharging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero;
• and
• second means for clamping the voltage level of the panel capacitance upon the inductor current reaching zero during discharging of the panel capacitance.

An energy efficient driver circuit for driving display panels having panel electrodes and panel capacitance, said driver circuit comprising:

• an inductor coupled to said panel electrodes for charging and discharging the panel capacitance;
• means for charging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero;
• and
• means for discharging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero.

An energy efficient sustainer circuit for driving display panels having panel electrodes and panel capacitance, said sustainer circuit comprising

• an inductor coupled to said panel electrodes for charging and discharging the panel capacitance;
• means for charging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero;
• and
• first means for clamping the voltage level of the panel capacitance upon the inductor current reaching zero during charging of the panel capacitance;
• means for discharging the panel capacitance through said inductor, initially while storing energy in said inductor until the magnitude of the inductor current reaches a maximum, and secondly while removing the stored energy from said inductor until the inductor current reaches zero;
• and
• second means for clamping the voltage level of the panel capacitance upon the inductor current reaching zero during discharging of the panel capacitance.

An energy efficient driver circuit for driving display panels having panel electrodes and panel capacitance, said driver circuit comprising:

• an inductor coupled to said panel electrodes for charging and discharging said panel capacitance respectively to and from a desired voltage level magnitude;
• first switch means coupled to said inductor to enable said panel capacitance to charge through said inductor from a first voltage level (a) initially to an intermediate voltage level magnitude which is about one-half the desired voltage level magnitude, while storing energy in said inductor, and (b) then to said desired voltage level magnitude, while removing said stored energy from said inductor;
• and
• second switch means coupled to said inductor to enable said panel capacitance to discharge through said inductor from said desired voltage level magnitude (a) initially to an intermediate voltage level magnitude which is about one-half the desired voltage level magnitude, while storing energy in said inductor, and (b) then to said first voltage level magnitude, while removing said stored energy from said inductor.