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US 5,081,380 AGranted
Temperature self-compensated time delay circuits
AssigneeAdvanced Micro Devices, Inc.
InventorKou-Su Chen
Life of this patent
Estimating the term…
Abstract
A constant time delay circuit which is insensitive to variations in temperature and has no D.C. power disipation includes a temperature-insensitive reference current source (12) for dynamically charging and discharging a capacitive load (M5), a polysilicon resistor (16), and at least one time delay control circuit (14) to produce a constant time delay. In an alternate embodiment, there is provided a temperature self-compensated programmable delay circuit which includes electrically programmable resistor means (30) for adjusting the total resistance in a temperature-insensitive reference current source (12b). As a result, the amount of the reference current is controlled so as to obtain a desired delay time.
Claims20
A temperature self-compensated constant time delay circuit comprising:
- reference current source means (12) for generating a first stable reference current (IREF1) at a first node (102) and a second stable reference current (IREF2) at a second node (104) which are insensitive to variations in temperature over a wide range;
- said reference current source means (12) including a pair of first and second N-channel transistors (MN1, MN2) and a current mirror arrangement formed of first and second P-channel transistors (MP1, MP2), the gates of said first and second N-channel transistors (MN1, MN2) being connected together and to the drain of said first N-channel transistor (MN1), said first N-channel transistor (MN1) having its drain connected to the second node (104) and its source connected to a ground potential, said second N-channel transistor (MN2) having its drain connected to the first node (102) and its source connected to a third node (106);
- the gates of said first and second P-channel transistors (MP1, MP2) being connected together and to the drain of the second P-channel transistor (MP2), said first P-channel transistor (MP1) having its source connected to a supply potential and its drain connected to the second node (104), said second P-channel transistor (MP2) having its source also connected to the supply potential and its drain connected to the first node (102);
- a polysilicon resistor (16) having its one end connected to the third node (106) and its other end connected to the ground potential;
- at least one time delay control circuit (14) including a P-channel MOS current-sourcing transistor (M1), a first switching transistor (M2), a second switching transistor (M3) and an N-channel MOS current-sinking transistor (M4), said current-sourcing transistor (M1) having its source connected to the supply potential, its gate connected to the first node (102) and its drain connected to the source of said first switching transistor (M2), said current-sinking transistor (M4) having its drain connected to the source of said second switching transistor (M3), its gate connected to the second node (104), and its source connected to the ground potential, the gates of said first and second switching transistors (M2, M3) being connected together and to an input terminal for receiving an input logic signal (VIN), the drains of said first and second switching transistors (M2, M3) being connected together and to a fourth node (110);
- said P-channel MOS current-sourcing transistor (M1) and said second P-channel transistor (MP2) defining a second current mirror arrangement so that the current flowing through said P-channel current-sourcing transistor (M1) will be equal to said first reference current (IREF1);
- said N-channel MOS current-sinking transistor (M4) and said first N-channel transistor (MN1) defining a third current mirror arrangement so that the current flowing through said N-channel current-sinking transistor (M4) will be equal to said second reference current (IREF2);
- and
- said time delay control circuit (14) further including capacitive load means (M5) coupled between said fourth node (110) and the ground potential, said capacitive load means being charged by said first reference current from said first node and being discharged by said first reference current from said second node to produce a constant delay time at said fourth node (110).
6 more elements
A temperature self-compensated programmable time delay circuit comprising:
- reference current source means (12) for generating a first stable reference current (IREF1) at a first node (102) and a second stable reference current (IREF2) at a second node (104) which are insensitive to variations in temperature over a wide range;
- said reference current source means (12) including a pair of first and second N-channel transistors (MN1, MN2) and a current mirror arrangement formed of first and second P-channel transistors (MP1, MP2), the gates of said first and second N-channel transistors (MN1, MN2) being connected together and to the drain of said first N-channel transistor (MN1), said first N-channel transistor (MN1) having its drain connected to the second node (104) and its source connected to a ground potential, said second N-channel transistor (MN2) having its drain connected to the first node (102) and its source connected to a third node (106);
- the gates of said first and second P-channel transistors (MP1, MP2) being connected together and to the drain of the second P-channel transistor (MP2), said first P-channel transistor (MP1) having its source connected to a supply potential and its drain connected to the second node (104), said second P-channel transistor (MP2) having its source also connected to the supply potential and its drain connected to the first node (102);
- electrically programmable resistor means (30) coupled between said third node (106) and the ground potential for adjusting the total resistance value;
- at least one time delay control circuit (14) including a P-channel MOS current-sourcing transistor (M1), a first switching transistor (M2), a second switching transistor (M3) and an N-channel MOS current-sinking transistor (M4), said current-sourcing transistor (M1) having its source connected to the supply potential, its gate connected to the first node (102) and its drain connected to the source of said first switching transistor (M2), said current-sinking transistor (M4) having its drain connected to the source of said second switching transistor (M3), its gate connected to the second node (104), and its source connected to the ground potential, the gates of said first and second switching transistors (M2, M3) being connected together and to an input terminal for receiving an input logic signal (VIN), the drains of said first and second switching transistors (M2, M3) being connected together and to a fourth node (110);
- said P-channel MOS current-sourcing transistor (M1) and said second P-channel transistor (MP2) defining a second current mirror arrangement so that the current flowing through said P-channel current-sourcing transistor (M1) will be equal to said first reference current (IREF1);
- said N-channel MOS current-sinking transistor (M4) and said first N-channel transistor (MN1) defining a third current mirror arrangement so that the current flowing through said N-channel current-sinking transistor (M4) will be equal to said second reference current (IREF2);
- and
- said time delay control circuit (14) further including capacitive load means (M5) coupled between said fourth node (110) and the ground potential, said capacitive load means being charged by said first reference current from said first node and being discharged by said second reference current from said second node to produce a constant delay time at said fourth node (110).
6 more elements
An electrically programmable reference current source for generating a first stable reference current (IREF1) at a first node and a second stable reference current (IREF2) at a second node which are insensitive to variations in temperature over a wide range, said reference current source comprising:
- a pair of first and second N-channel transistors (MN1, MN2);
- a current mirror arrangement formed of first and second P-channel transistors (MP1, MP2);
- the gates of said first and second N-channel transistors (MN1, MN2) being connected together and to the drain of said first N-channel transistor (MN1), said first N-channel transistor (MN1) having its drain connected to the second node (104) and its source connected to the ground potential, said second N-channel transistor (MN2) having its drain connected to the first node (102) and its source connected to a third node (106);
- the gates of said first and second P-channel transistors (MP1, MP2) being connected together and to the drain of the second P-channel transistor (MP2), said first P-channel transistor (MP1) having its source connected to a supply potential and its drain connected to the first node (104), said first P-channel transistor (MP2) having its source also connected to the supply potential and its drain connected to the first node (102);
- and
- electrically programmable resistor means (30) coupled between said third node (106) and the ground potential for adjusting the total resistance value.
3 more elements
Dependencies are inferred from the claim text.