Bidirectional FIFO buffer having reread and rewrite means

A FIFO buffer all integrated into a single device, the buffer comprising in combination:

• read pointer counter means (254) for developing signals representing a random access memory array read address;
• write pointer counter means (266) for developing signals representing a random access memory array write address, said write pointer counter means being responsive to an externally generated re-write signal and operative to load a re-write address;
• re-write pointer register means (286) connected to said write pointer counter means, said re-write pointer register means for developing signals representing said rewrite address, said re-write pointer register means being responsive to a load re-write pointer command signal and operative to load said random access memory array write address;
• and,
• dual port, random access memory array means (400) having a set of data inputs, a set of data outputs, a set of write addressing inputs connected to said write pointer counter means and a set of read addressing inputs connected to said read pointer counter means, said random access memory array means for receiving at said data inputs externally generated signals representing a word of data, for storing said received data word at said random access memory array write address, and for developing at said data outputs signals representing the word of data stored at said random access memory array read address.

A FIFO buffer system all integrated into a single device, the system comprising in combination:

• an A bust (140);
• a B bus (144);
• a FIFO buffer (110) connected to said A bus, said FIFO buffer including,
• write pointer counter means (204) for developing signals representing a random access memory array write address,
• read pointer counter means (216) for developing signals representing a random access memory array read address, said read pointer counter means being responsive to an externally generated re-read signal and operative to load a re-read address,
• re-read pointer register means (236) connected to said read pointer counter means, said re-read pointer register means for developing signals representing said re-read address, said re-read pointer register means being responsive to an externally generated load re-read pointer command signal and operative to load said random access memory array read address, and
• dual port, random access memory array means (300) having a set of data inputs connected to said A bus, a set of data outputs, a set of write addressing inputs connected to said write pointer counter means, and a set of read addressing inputs connected to said read pointer counter means, said random access memory array means for receiving at said data inputs externally generated signals representing an m-bit word, for storing said received m-bit at said random access memory array write address, and for developing at said data outputs signals representing said m-bit word stored at said random access memory array read address, where m is a positive integer of at least sixteen;
• and,
• multiplexer means (112) connected to said FIFO buffer and to said B bus, said multiplexer means for receiving each of said stored m-bit words and for developing on said B bus signals representing, first, an n-bit portion and, next, another, different, n-bit portion of each of said stored m-bit words where n is a positive integer of at least eight;
• and,

A FIFO buffer systems all integrated into a single device, the system comprising in combination:

• an A bus (140);
• a B bus (144);
• converter means (116) connected to said B bus, said converter means for receiving signals representing a succession of n-bit works, for assembling at least two of said received n-bit words into one m-bit word, and for developing signals representing, in succession, said assembled m-bit words, where m is a positive integer of at least sixteen and where n is a positive integer of at least eight;
• and,
• a FIFO buffer (114) connected to said converter means and to said A bus, said FIFO buffer including,
• read pointer counter means (254) for developing signals representing a random access memory array read address,
• write pointer counter means (266) for developing signals representing a random access memory array write address, said write pointer counter means being responsive to an externally generated re-write signal and operative to load a re-write address,
• re-write pointer register means (286) connected to said write pointer counter means, said re-write pointer register means for developing signals representing said re-write address, and re-writed pointer register means being responsive to an externally generated load re-write pointer command signal and operative to load said random access memory array write address, and
• random access memory array means (400) connected to said converter means, to said write pointer counter means, to said read pointer counter means, and to said A bus, said random access memory array means for receiving each of said assembled m-bit words, for storing said received m-bit data word at said random access memory array write address and for developing on said A bus signals representing the m-bit data word stored at said random access memory array read address.