Flash EEPROM array with negative gate voltage erase operation

A method for reprogramming memory cells within a flash EEPROM array using Fowler-Nordheim tunneling for erasure of preprogrammed cells and hot electron injection for the reprogramming of the cells, the array being defined on a semiconductor substrate, each cell including an N-type source region, a P-type channel, an N-type drain region, a floating gate positioned over the channel and a control gate positioned over the floating gate, the method comprising the erasure steps of:

• applying a reference voltage of zero volts to the substrate of the array;
• applying a positive voltage in the range of approximately zero volts to 5 volts to the source regions of preselected memory cells in the array;
• and
• applying a negative voltage in the range of approximately -12 volts to -17 volts to the control gates of the preselected memory cells in the array thereby to induce Fowler-Nordheim tunneling of electrons from the floating gates of the preselected memory cells to their source regions;
• and the method further comprising the post-erasure steps of:
• applying a positive voltage to the drain regions of cells that are to be programmed;
• and
• applying a positive voltage to the control gates of cells that are to be programmed.

A method for bypassing erasure of redundant cells on an integrated memory circuit having a predefined addressable memory space and comprising plural rows of flash-erasable electrically-programmable memory cells, each of the cells having an N-type source region, a P-type channel region, an N-type drain region, a floating gate and a control gate the method comprising:

• providing more rows of memory cells on the integrated circuit than necessary for filling the predefined memory space of the integrated memory circuit;
• designating one or more of the rows as rows to be bypassed during normal addressing operations;
• applying a negative erase voltage to the control gates of memory cells in rows which are not to be bypassed;
• and
• providing a non-negative voltage to the control gate of memory cells in rows which are to be bypassed to thereby disable erasure of those memory cells.

A method for flash erasing the memory cells of a flash EEPROM array formed on an integrated circuit having only a V.sub.cc pin and a ground pin for supplying power from an external source into the integrated circuit, the integrated circuit including rows of memory cells and a common source line extending along the rows, each cell including a source region coupled to the common source line and a control gate, the method comprising the steps of:

• generating a source voltage of a same polarity as that of an external voltage present on the V.sub.cc pin;
• applying the source voltage to source regions of the memory cells during flash erasure;
• generating a gate voltage within the integrated circuit of a polarity opposite to the source voltage;
• and
• applying the opposite polarity gate voltage to the control gates of the memory cells during flash erasure.

An integrated memory circuit having a program mode, a flash-erase mode and a read mode, the circuit comprising:

• a substrate;
• a matrix of electrically programmable and electrically erasable memory cells defined on the substrate, the cells being organized in rows and columns, each memory cell including a source region, a drain region a channel region interposed between the source and drain regions, a floating gate insulatively disposed over the channel region and a control gate insulatively disposed over the floating gate;
• a common source line connected to the source regions of memory cells in at least one row of said matrix;
• a plurality of word lines each extending along a corresponding row of said matrix and each connected to the control gates of memory cells in its corresponding row;
• a plurality of bit lines each extending along a corresponding column of said matrix and each connected to the drain regions of memory cells in its corresponding column;
• source line switching means, connected to the common source line, for switchingly connecting the common source line to an erase-mode source voltage during the flash-erase mode, to a program-mode source voltage during the program mode, and to a read-mode source voltage during the read mode;
• a plurality of word line switching means each connected to a respective one of said word lines for switchingly connecting the respective word line to either an erase-enable (E) gate voltage or an erase-inhibit (EI) gate voltage during the flash-erase mode, to either a program-enable (P) gate voltage or a program-inhibit (PI) gate voltage during the program mode and to either a read-enable (R) gate voltage or a read-inhibit (RI) gate voltage during the read mode;
• and
• a plurality of bit line switching means each connected to a respective one of said bit lines for switchingly connecting the respective bit line to an erase-enable (E) drain impedance during the flash-erase mode, to either a program-enable (P) drain voltage or a program-inhibit (PI) drain voltage during the program mode and to either a read-enable (R) drain voltage or a read-inhibit (RI) drain voltage during the read mode;
• wherein said erase-enable gate voltage is nonzero and of opposite polarity to said erase-mode source voltage, the difference between the erase-enable gate voltage and the erase-mode source voltage being sufficient to substantially remove charge from the floating gates of memory cells whose control gates are at the erase-enable gate voltage;
• and
• wherein the difference between the erase-inhibit gate voltage and the erase-mode source voltage is insufficient to substantially remove charge from the memory cells whose control gates are at the erase-inhibit gate voltage during the flash-erase mode.

An array of flash-erasable electrically-programmable memory cells, the array comprising:

• a substrate;
• a common source line defined in the substrate;
• a wordline running parallel to the source line;
• a row of erasably programmable transistors each having a source region connected to the common source line, a control gate connected to the wordline, a floating gate for storing charge carriers, a thin dielectric separating the floating gate from the source region such that charge carriers may tunnel from the floating gate to the source region, a channel region and a drain region;
• a plurality of bit lines running orthogonally to the wordline, each bit line being connected to the drain region of a corresponding one of said transistors;
• first voltage supply means defined on the substrate to charge said common source line to a first voltage level for inducing stored charge carriers to tunnel from the floating gates of said transistors to their respective source regions;
• and
• second voltage supply means defined on the substrate to charge the wordline to a second voltage level for further inducing stored charge carriers to tunnel from the floating gates of said transistors to their respective source regions.

A method for inhibiting erasure in one or more preselected rows of a flash-EEPROM array during flash erasure where each row of the array has a plurality of memory cells and where each cell has a control gate coupled to a word line extending along the cell's row and a source region coupled to a common source line, the method comprising the steps of:

• applying a first erase-enabling voltage to the common source line;
• applying a second erase-enabling voltage to the word lines of rows whose cells are to be flash erased, the difference between said first and second erase-enabling voltages being sufficient to enable erasure of the to-be-erased cells;
• and
• developing an erase-inhibiting voltage on the word lines of rows whose cells are not to be erased, the difference between said first erase-enabling voltage and said erase-inhibiting voltage being insufficient to enable erasure of the not-to-be erased cells.

A method for flash erasing an array of EEPROM memory cells provided on an integrated circuit substrate where each memory cell includes a stacked-gate transistor having a channel region, a floating gate uniformly spaced above the channel region by a tunneling dielectric, a control gate insulatively disposed above the floating gate, a source region at one side of the channel region and a drain region at an opposed second side of the channel region and where the integrated circuit substrate receives power through a ground terminal and a Vcc terminal provided for connecting the substrate to an external power supply, the method comprising the steps of:

• applying simultaneously to the source regions of a plurality of said memory cells, a source voltage of a magnitude sufficiently low to suppress avalanche-dominated conduction of current between the source regions of said cells and the substrate;
• applying simultaneously to the control gates of said plurality of memory cells, an erase-enabling gate voltage of sufficient magnitude such that the combination of said source voltage and said erase-enabling gate voltage is sufficient to induce tunneling of a substantial number of charge carries between the floating gates and source regions of said plural memory cells to thereby erase charge from said floating gates;
• and
• supplying current through said Vcc terminal for developing both the source voltage and the erase-enabling voltage.

A method for minimizing hot hole trapping in a flash-erasable EPROM array where the array comprises a plurality of stacked-gate transistors defined on a semiconductor substrate, each transistor having a channel region, a floating gate insulatively spaced apart from the channel region by a tunneling dielectric of uniform thickness, a control gate insulatively disposed above the floating gate, a source region at one side of the channel region and a drain region at an opposed second side of the channel region,

• the method comprising the steps of, during flash-erasure of the array;
• applying simultaneously to the source regions of a plurality of said transistors, a source voltage of a magnitude sufficiently low to suppress avalanche-dominated conduction of current between the source regions of said cells and the substrate to thereby suppress the generation of hot holes which may become trapped in said tunneling dielectric;
• applying simultaneously to the control gates of said plurality of transistors, an erase-enabling gate voltage of sufficient magnitude such that the combination of said source voltage and said erase-enabling gate voltage is sufficient to induce tunneling of a substantial number of charge carries between the floating gates and source regions of said plural memory cells to thereby erase charge from said floating gates;
• and
• supplying current from a single power supply for developing both the source voltage and the erase-enabling gate voltage.

A method for minimizing power consumption in a flash-erasable EPROM array where the array comprises a plurality of stacked-gate transistors defined on a semiconductor substrate, each transistor having a channel region, a floating gate insulatively spaced apart from the channel region by a tunneling dielectric of uniform thickness, a control gate insulatively disposed above the floating gate, a source region at one side of the channel region and a drain region at an opposed second side of the channel region,

• the method comprising the steps of, during flash-erasure of the array:
• applying simultaneously to the source regions of a plurality of said transistors, a source voltage of a magnitude sufficiently low to suppress avalanche-dominated conduction of current between the source regions of said cells and the substrate to thereby suppress the generation of hot holes;
• applying simultaneously to the control gates of said plurality of transistors, an erase-enabling gate voltage of sufficient magnitude such that the combination of said source voltage and said erase-enabling gate voltage is sufficient to induce tunneling of a substantial number of charge carries between the floating gates and source regions of said plural memory cells to thereby erase charge from said floating gates;
• and
• supplying current from a single power supply for developing both the source voltage and the erase-enabling gate voltage.

A method for measuring the relation between source current (I.sub.s), source voltage (V.sub.s) and control gate voltage during tunneling of charge carriers from a normally-floating charge-storing gate of a memory cell to a source region of the cell, the method comprising:

• attaching a current injecting line to the normally-floating gate;
• coupling a first variable voltage source to the current injecting line to produce a variable float voltage (V.sub.F) thereat;
• coupling a second variable voltage source to the source region of the cell to produce a variable source voltage (V.sub.S) thereat;
• varying the source voltage (V.sub.S) over a predetermined range;
• and
• measuring the amount of current (I.sub.S) consumed by the source region.