Parallel string processor and method for a minicomputer

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising:

• a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word;
• and
• a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said first logic level, thus identifying the most significant byte of said first data word that matches the corresponding byte of said second data word.

A parallel byte string processor that finds the location of matching bytes in first and second data words, each data word having a predetermined number of data bytes, said parallel byte processor comprising:

• a first circuit that performs an exclusive-OR operation on said first and second data words on a byte-by-byte basis, and provides an output bit corresponding to each byte of said first data word, each said output bit having first and second logic levels such that an output bit has said first logic level when the corresponding byte in said first data word matches the corresponding byte in said second data word and has said second logic level when the corresponding byte in said first data word does not match the corresponding byte in said second data word;
• and
• a second circuit that receives said output bits from said first circuit, said second circuit providing a digital output value that identifies the location of an output bit from said first circuit that has a predetermined positional characteristic with respect to the other output bits from said first circuit which is the location of the most significant bit of said output bits having said second logic level, thus identifying the most significant byte of said first data word that does not match the corresponding byte of said second data word.

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word having data of unknown content in said bytes and that finds the location of a byte in said first multiple-byte data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first multiple-bytes data word, comprising:

• a first circuit that provides an output signal for each byte of said first multiple-byte data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic;
• and
• a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first multiple-byte data word having said selected positional characteristic.

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising:

• a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic;
• and
• a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, and wherein said selected content characteristic of a byte in said first data word is equal to the corresponding byte of said second data word.

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising:

• a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic;
• and
• a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte having said selected content characteristic.

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising:

• a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic;
• and
• a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte not having said selected content characteristic.

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising:

• a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic;
• and
• a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte having said selected content characteristic that is less significant than the most significant byte not having said selected content characteristic.

A parallel byte string processor that performs a data manipulation operation on each of the bytes of a first multiple-byte data word and that finds the location of a byte in said first data word having a selected content characteristic and a selected positional characteristic with respect to other bytes in said first data word, comprising:

• a first circuit that provides an output signal for each byte of said first data word, wherein for each byte, the respective output signal has a first logic level when the byte has said selected content characteristic and has a second logic level when the byte does not have said selected content characteristic;
• and
• a second circuit that receives the output signals from said first circuit, said second circuit providing a digital output value that identifies the location of an output signal from said first circuit that has a selected one of said first and second logic levels and that corresponds to a byte in said first data word having said selected positional characteristic, wherein said selected positional characteristic is the most significant byte not having said selected content characteristic that is less significant than the most significant byte having said selected content characteristic.