FIFO control architecture and method for buffer memory access arbitration

A FIFO control architecture for interfacing multiple external peripheral devices to a dynamic RAM buffer memory comprising at least two I/O channels, each of the channels having:

• a FIFO connecting the associated external peripheral device and the DRAM buffer memory;
• first memory pointer means for defining an address in the buffer memory for transfer of data between the peripheral device and the buffer memory;
• means for establishing and tracking a transfer count between the peripheral device and the buffer memory;
• means for determining the number of data bytes in the FIFO;
• means for generating a first level data request responsive to a first predetermined number of bytes in the FIFO and a second level data request responsive to a second predetermined number of bytes in the FIFO;
• and
• a first enabling means for enabling the FIFO for data transfer to the buffer memory address in the first pointer means;
• a DRAM refresh circuit connected to the buffer memory and having
• means for timing a desired refresh interval for a page of the DRAM and signalling expiration of the interval;
• a counter incremented by the signal from the timing means;
• means for generating a first level refresh request signal upon expiration of the timer and a second level refresh request signal upon the counter reaching a predetermined count;
• a second memory address pointer means for designating the page of the DRAM to be refreshed;
• and
• a second enabling means for enabling the refresh circuit to address the page designated by the second pointer incrementally for the number of counts in the counter;
• and
• an arbiter state machine connected to the first and second enabling means, the arbiter state machine further receiving and responsive to the first and second level data request signals and the first and second level refresh request signals for enabling the first and second enabling means thereby selectively enabling the FIFOs and the refresh circuit based on a predetermined priority of the external peripheral devices and the level of request signals.