Method and apparatus for mapping a digital signal carrier to another
AssigneeTelecommunications Research Laboratories
InventorThomas E. Moore
Life of this patent
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Abstract
A DS-3 to 28 VT1.5 SONET Interface Circuit is shown, without using standard intermediate DS-2 and DS-1 Desynchronizer Phase-Lock Loops. The elimination of DS-2 and DS-1 Desynchronizer Phase Lock Loops results in a significant reduction in cost and complexity of SONET interface circuits for the existing asynchronous digital multiplex hierarchy.
Claims4
A process for the mapping of a first digital signal carrier carrying a first multiplexed digital signal to a second digital signal carrier comprising:
- demultiplexing the first digital signal to produce a second digital signal and to derive a gapped clock;
- writing the second digital signal to an elastic store using the gapped clock;
- and
- reading the second digital signal from the elastic store.
Apparatus for the mapping of a first digital signal carrier carrying a first digital signal to a second digital signal carrier comprising:
- a demultiplexer for demultiplexing the first digital signal to produce a second digital signal;
- gapping means for gapping the first digital signal carrier to derive a gapped clock;
- writing means for writing the second digital signal to an elastic store using the gapped clock;
- and
- reading means for reading the second digital signal from the elastic store.
Apparatus for mapping a DS-3 digital signal to a SONET signal, the apparatus comprising:
- a first demultiplexer for demultiplexing the DS-3 signal to generate a DS-2 signal and to generate a gapped DS-2 clock;
- a second demultiplexer to demultiplex the DS-2 signal to generate a DS-1 signal and to generate a gapped DS-1 clock;
- and
- bit stuffing means for bit stuffing the DS-1 signal to create a SONET signal.
Dependencies are inferred from the claim text.