High order sigma delta oversampled analog-to-digital converter integrated circuit network with minimal power dissipation and chip area requirements

A third order sigma delta analog-to-digital converter network formed on an integrated circuit chip, comprising:

• a second order modulator including first and second integrators coupled in cascade such that the output of said first integrator is coupled to the input of said second integrator;
• an analog-to-digital converter, the output of said second integrator being coupled to the input of said analog-to-digital converter for converting an analog input signal into a first digital output signal corresponding to the analog input signal plus a second order differential quantization noise component;
• means responsive to the output signal of said analog-to-digital converter for generating an analog output signal corresponding to said first digital output signal less any quantization noise of said second order modulator;
• a first order modulator comprising a third integrator coupled to the output of said second integrator and an analog-to-digital converter coupled to the output of said third integrator for converting the analog output signal of said second integrator into a second digital output signal corresponding to said analog output signal plus a first order differential quantization noise component;
• and
• means responsive to said first and second digital output signals of said second order and first order modulators, respectively, for eliminating the first and second order differential quantization noise components therefrom and generating a digital output signal corresponding to the analog input signal,
• each of said second and third integrators occupying less area of said chip than said first integrator.

On an integrated circuit chip, a third order sigma delta analog-to-digital converter network, comprising:

• a second order modulator including first and second integrators coupled in cascade such that the output of said first integrator is coupled to the input of said second integrator, a first comparator coupled to the output of said second integrator for providing a first digital output signal, and a first switched reference voltage source responsive to said first comparator;
• a first order modulator including a third integrator coupled to the output of said second integrator, a second comparator coupled to the output of said third integrator for providing a second digital output signal, and a second switched reference voltage source responsive to said second comparator;
• said third integrator responding to the output signal of said second integrator and to said second switched reference voltage source to provide an analog output signal to said second comparator;
• a digital multiplier for multiplying said second digital output signal from said first order modulator;
• a digital subtractor for providing a digital difference signal between the digital output signal of said second order modulator and the multiplied digital output signal of said first order modulator;
• a digital double differentiator coupled to the output of said digital subtractor for twice differentiating said digital difference signal to produce a resultant digital signal including a second order differential noise component from said second order modulator and a third order differential noise component from said first order modulator;
• a digital adder for adding said first digital output signal and said resultant digital signal to produce a third digital output signal;
• and
• a digital decimation filter responding to said third digital output signal,
• each of said integrators comprising a differential amplifier, at least one input capacitor and at least one feedback capacitor,
• each differential amplifier of said second and third integrators and the capacitors respectively coupled thereto occupying less area of said chip than the differential amplifier of said first integrator and the capacitors respectively coupled thereto so as to maintain power dissipation in said second and third integrators below power dissipation in said first integrator.