Differential amplifying circuit operable at high speed

A differential amplifier circuit comprising:

• a first input port for receiving an input voltage;
• a first field effect transistor (FET) having a drain, a source and a gate which is responsive to said input voltage to control conduction between said drain and said source;
• a second FET having a drain, a source and a gate which is responsive to a first reference voltage to control conduction between said drain and said a source of said second FET, said source of said second FET being connected to said source of said first FET;
• a constant current source connected to said sources of said first and second FETs for supplying a constant current from said sources of said first and second FETs to a low potential power source;
• a third FET having a drain connected to a high potential power source and having a source connected to a first output port to act as a load, said third FET having a gate connected to a first node which is connected to said drain of said first FET;
• a fourth FET having a drain connected to said high potential power source and having a source connected to a second output port to act as a load, said fourth FET having a gate connected to a second node which is connected to said drain of said second FET;
• a fifth FET having a drain connected to said source of said third FET and a source connected to said first node, said fifth FET having a gate which is responsive to a second reference voltage to control conduction between said drain and said source of said fifth FET;
• and
• a sixth FET having a drain connected to said source of said fourth FET and having a source connected to said second node, said sixth FET having a gate which is connected to said gate of said fifth FET and which is responsive to said second reference voltage to control conduction between said drain and said source of said sixth FET, said second reference voltage being independent of the conduction of said first through sixth FETs.