Apparatus and method for recovering from missing page faults in vector data processing operations

A method of operating a digital data processing unit connected to a main memory unit including a plurality of storage locations, each identified by a physical address, for storing vector operands and vector instructions, one type of said vector instructions being a computational instruction for initiating a computational operation, and another type of said vector instructions being a transfer vector instruction for initiating a transfer operation and identifying a virtual address, said method comprising the steps of:

• A. iteratively retrieving vector instructions from said main memory unit and performing an instruction issue operation to transfer an instruction of said computational instruction type to a vector execution unit for processing and to a vector address generating unit if the instruction is of the transfer vector instruction type;
• B. enabling said vector address generating unit to perform, in response to receipt of an instruction of the transfer vector instruction type, an address translation operation to (1) generate a physical address in response to the virtual address identified by the transfer vector instruction corresponding to a physical address in said main memory unit, to enable a vector operand to be transferred between the storage location identified by said physical address and said vector register, and (2) generate a page fault indication if said virtual address identified by said transfer vector instruction does not correspond to a physical address in said main memory unit;
• C. responding to a page fault indication from said vector address generating unit resulting from one of said vector instructions by (1) terminating performing instruction issue operations while permitting said execution unit to continue to perform vector operations identified by other ones of said vector instructions that have already been issued, and (2) generating restart information to identify the vector instruction which resulted in the page fault indication;
• D. establishing in said main memory a physical address corresponding to the virtual address which gave rise to said page fault indication, and
• E. using said restart information to process the vector instruction which resulted in the page fault indication using the established physical address.

A digital data processing system including a digital data processing unit connected to a main memory unit including a plurality of storage locations, each identified by a physical address, for storing vector operands and vector instructions one type of said vector instructions being a computational instruction for initiating a computational operation, and another type of said vector instructions being a transfer vector instruction for initiating a transfer operation and identifying a virtual address, said digital data processing unit comprising:

• A. a vector register for storing vector operands;
• B. a vector execution unit for performing vector operations identified by vector instructions of the computational type in connection with vector operands in said vector register;
• C. a vector address generating unit for performing, in response to receipt of an instruction of the transfer vector instruction type, and address translation operation to (1) generate a physical address in response to the virtual address identified by the transfer vector instruction corresponding to a physical address in said main memory unit, to enable a vector operand to be transferred between the storage location identified by said physical address and said vector register, and (2) generate a page fault indication if said virtual address identified by said transfer vector instruction does not correspond to a physical address in said main memory unit;
• and
• D. an instruction issue unit for iteratively retrieving vector instructions from said main memory unit and performing an instruction issue operation to transfer an instruction of said computational instruction type to said vector execution unit and to transfer an instruction of said transfer vector instruction type to said vector address generating unit to enable it to perform the address translation operation, said instruction issue unit being response ti a page fault indication from said vector address generating unit resulting from one of said vector instruction to (1) terminate performing instruction issue operations while permitting said execution unit to continue to perform vector operations identified by other ones of said vector instructions that have already been issued and (2) generate restart information to identify the vector instruction which resulted in the page fault indication.

A digital data processing unit for connection to a main memory unit including a plurality of storage locations, each identified by a physical address, for storing vector operands and vector instructions, one type of said vector instructions being a computational instruction for initiating a computational operation, and another type of said vector instructions being a transfer vector instruction for initiating a transfer operation and identifying a virtual address, said main memory unit further including a page table entry corresponding to said virtual address, said page table entry including access rights information and operational rights information, said digital data processing unit comprising:

• A. a vector register for storing vector operands;
• B. a vector execution unit for performing vector operations identified by vector instructions of the computational type in connection with vector operands in said vector register;
• C. a vector address generating unit including:
• i. means responsive to receipt of an instruction of the transfer vector instruction type, for retrieving said page table entry;
• ii. page fault test means for using the retrieved page table entry to determine whether said virtual address identified by said transfer vector instruction corresponds to a physical address in said main memory unit, and for generating a page fault indication if said virtual address identified by said transfer vector instruction does not correspond to a physical address in said main memory unit;
• iii. access rights test means for testing the access rights information in the retrieved page table entry to determine whether access to the virtual address identified by said page table entry is permitted and for initiating a predetermined operation if it is not;
• iv. operational rights test means for testing the operational rights information in the retrieved page table entry to determine whether a predetermined operation may be performed in connection with information identified by the virtual address identified by said page table entry and for initiating a predetermined operation if it is not;
• and
• v. means for performing an address translation operation to generate a physical address in response to the virtual address identified by the transfer vector instruction corresponding to a physical address in said main memory unit, to enable a vector operand to be transferred between the storage location identified by said physical address and said vector register, if said page fault test means determines that the virtual address corresponds to a physical address in said main memory unit, said access rights test mean determines that the access to the virtual address is permitted, and said operational rights test means determines that the predetermined operation may be performed;
• and
• D. an instruction issue unit for iteratively retrieving vector instructions form said main memory unit and performing an instruction issue operation to transfer an instruction of said computational instruction type to said vector execution unit and to transfer an instruction of said transfer vector instruction type to said vector address generating unit to enable it to perform the address translation operation, said instruction issue unit being responsive to a page fault indication from said vector address generating unit resulting from one of said vector instructions to (1) terminate performing instruction issue operations while permitting said execution unit to continue to perform vector operations identified by other ones of said vector instructions that have already been issued, and (2) generate a restart information frame on a kernel stack, to identify the vector instruction which resulted in the page fault indication, said restart information frame including an indicator indicating whether it had established a previous restart information frame on said kernel stack;
• E. a program module for enabling establishment in said main memory of a physical address corresponding to the virtual address which gave rise to said page fault indication;
• and
• F. a faulted instruction processing program module enabling processing of the restart information frame on said kernel stack, the faulted instruction process program module using the indicator to enable processing of said previous restart information frame.

A digital data processing unit for connection to a main memory unit including a plurality of storage locations, each identified by a physical address, for storing (i) vector operands an vector instructions one type of said vector instructions being a computational instruction for initiating a computational operation, and another type of said vector instructions being a transfer vector instruction for initiating a transfer operation and identifying a virtual address, and (ii) scalar operands and scalar instructions one type of said scalar instructions being a second computational instruction for initiating a second computational operation, and another type of said scalar instructions being a transfer scalar instruction for initiating a scalar transfer operation and identifying a second virtual address, aid main memory unit further including a page table entry corresponding to each of said virtual addresses, each said page table entry including access rights information and operational rights information, said digital data processing unit comprising:

• A. a vector register for storing vector operands;
• B. a vector execution unit for performing vector operations identified by vector instructions of the computational type in connection with vector operands in said vector register;
• C. a scalar register for storing scalar operands;
• D. a scalar execution unit for performing scalar operations identified by a scalar instruction of the computational type in connection with scalar operands in said scalar register;
• E. a vector address generating unit including:
• i. vector page table entry retrieving means responsive to receipt of an instruction of the transfer vector instruction type, for retrieving a said page table entry;
• ii. vector page fault rest means for using a retrieved page table entry to determine whether a virtual address identified by said received transfer vector instruction corresponds to a physical address in said main memory unit, and for generating a page fault indication if said virtual address identified by said received transfer vector instruction does not correspond to a physical address in said main memory unit;
• iii. vector access rights test means for testing the access rights information in the retrieved page table entry to determine whether access to the virtual address identified by said retrieved page table entry is permitted and for initiating a predetermined operation if it is not;
• iv. vector operational rights test means for testing the operational rights information in the retrieved page table entry to determine whether a predetermined operation may be performed in connection with information identified by the virtual address identified by said retrieved page table entry and for initiating a predetermined operation if it is not;
• and
• v. vector address translation means for performing an address translation operations to generate a physical address in response to the virtual address identified by the transfer vector instruction corresponding to a physical address in said main memory unit, to enable a vector operand to be transferred between the storage location identified by said generated physical address and said vector register, if said vector page fault test means determines that the virtual address identified by the transfer vector instruction corresponds to a physical address in said main memory unit, said vector access rights test means determines that the access to the virtual address identified by the transfer vector instruction is permitted, and said vector operational rights test mean determines that the predetermined operation may be performed;
• F. a scalar address generating unit including:
• i. scalar page table entry retrieval means responsive to receipt of an instruction of the transfer scalar instruction type, for retrieving a second said page table entry;
• ii. scalar page fault test means for using the second retrieved page table entry to determine whether said virtual address identified by said transfer scalar instruction corresponds to a physical address in said main memory unit, and for generating a page fault indication if said virtual address identified by said transfer scalar instruction does not correspond to a physical address in said main memory unit,
• iii. scalar access rights test means for testing the access rights information in the second retrieved page table entry to determine whether access to the virtual address identified by said second retrieved page table entry is permitted and for initiating a predetermined operation if it is not;
• iv. scalar operational rights test means for testing the operational rights information in the second retrieved page table entry to determine whether a predetermined operation may be performed in connection with information identified by the virtual address identified by said second retrieved page table entry and for initiating a second predetermined operation if it is not;
• and
• v. scalar address translation means for performing an address translation operation to generate a second physical address in response to the virtual address identified by the transfer scalar instruction corresponding to a physical address in said main memory unit, to enable a scalar operand to be transferred between the storage location identified by said second generated physical address and said scalar register, if said scalar page fault test means determines that the virtual address identified by the transfer scalar instruction corresponds to a physical address in said main memory unit, said scalar access rights test means determines that the access to the virtual address identified by the transfer scalar instruction is permitted, and said scalar operational rights test means determines that the second predetermined operation may be performed;
• G. an instruction issue unit for iteratively retrieving vector and scalar instructions from said main memory unit and performing an instruction issue operation to transfer (i) a vector instruction of said computational instruction type to said vector execution unit, (ii) a vector instruction of said transfer vector instruction type to said vector address generating unit to enable it to perform an address translation operation, (iii) a scalar instruction of said computational instruction type to said scalar execution unit, and (iv) a scalar instruction of said transfer scalar instruction type to said scalar address generating unit to enable it to perform an address translation operation, said instruction issue unit being responsive to a page fault indication from said vector address generating unit resulting from one of said vector instructions to (1) terminate performing instruction issue operations while permitting said execution unit to continue to perform vector operations identified by other ones of said vector instructions that have already been issued and (2) generate a restart information frame on a kernel stack, to identify the vector instruction which resulted in the page fault indication, said restart information frame including an indicator indicating whether it had established a previous restart information frame on said kernel stack;
• H. a program module for enabling the establishment in said main memory of a physical address corresponding to a virtual address which gave rise to a page fault indication;
• and
• I. a faulted instruction processing program module enabling processing of a restart information frame on said kernel stack, the faulted instruction process program module using the indicator to enable processing of a said previous restart information frame.