Monolithic double balanced mixer with high third order intercept point employing an active distributed balun

A double balanced mixer apparatus for mixing an RF input signal with a local oscillator (LO) signal to provide at an output an intermediate frequency (IF) signal with a high third order intercept point, comprising:

• a first active distributed input balun means having an input port for receiving said local oscillator signal (LO) and having first and second output ports,
• a double balanced resistive FET quad mixing means having first and second input ports for receiving said local oscillator signal, with said first input port coupled to said first output port of said first input balun, and said second input port coupled to said second output port of said first input balun, said mixing means having a third and a fourth input port for receiving said RF signal, and a first and second output port for providing an IF signal,
• a second active distributed input balun means having an input port for receiving said RF signal and having first and second output ports, with the first output port coupled to said third input port of said mixing means and said second output port coupled to said fourth input port of said mixing means,
• a combiner means having a first input port coupled to said first output port of said mixing means and a second input port coupled to said second output port of said mixing means to provide at an output of said combiner, said intermediate frequency signal (IF) relatively free of said LO and RF frequencies and having a high third order intercept point, `wherein said combiner means is a common gate combiner comprising:
• a first FET having dual source electrodes, a gate and a drain electrode with said first source electrode serving as said first input port, and with said second source electrode serving as said second input port, with said first source electrode directed to a point of reference potential via a second FET having the source electrode connected to the gate electrode and the drain electrode connected to said first source electrode of said first FET, and with said second source electrode directed to said point of reference potential via a third FET having the source electrode connected to the gate electrode and the drain electrode connected to said second source electrode of said first FET, with the gate electrode of said first FET adapted to receive a bias voltage and with the drain electrode of said first FET serving as said output port, with said drain electrode of said first FET coupled to a source of operating potential via a fourth FET having the source electrode connected to the gate electrode and connected to the drain electrode of said first FET and with the drain electrode of said fourth FET adapted to receive a source of operating potential.