Static random access memory with redundancy
AssigneeSamsung Electronics Co., Ltd.
InventorsHeui-Chul Park, Chang-Rae Kim
Life of this patent
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Abstract
A semiconductor memory device has normal memory blocks and redundant memory blocks for storing data therein. To elevate the redundancy efficiency, the memory device includes a number of normal block selectors for selecting the normal blocks, a number of redundant decoders for sensing a redundant mode on a basis of address signals provided thereto from an address buffer, a block selection decoder for generating a block selection signal by receiving an external address signal shaped, and a redundancy combining signal generator for generating a normal block selection signal and a redundant block selection signal by receiving output of the block selection decoder and output of the redundant decoder.
Claims21
A semiconductor memory device having at least one normal block and at least one redundant block, comprising:
- a plurality of normal block selectors for selecting corresponding ones of a plurality of normal blocks;
- a plurality of redundant decoders for sensing a redundant mode on a basis of address signals provided thereto from an address buffer;
- a block selection decoder for generating a block selection signal in response to reception of an external address signal;
- and
- redundancy combining means for generating a normal block selection signal and a redundant block selection signal, in dependence upon output of said block selection decoder and output of said redundant decoder;
- wherein several of said plurality of redundant decoders each comprise:
- fuse programming means for generating a fuse programming signal for replacing a defective one of said normal blocks with a redundant block;
- first logic means for performing logical NAND operations on a basis of said fuse programming signal and a pre-decoded redundant signal received from the address buffer;
- and
- first inverting means for inverting the output generated from said first logic means and for providing said inverted output signal to said redundancy combining means.
A semiconductor memory device, comprising:
- a plurality of normal block selector means for selecting corresponding ones of a plurality of normal blocks;
- a plurality of redundant decoding means for sensing a redundant mode on a basis of address signals provided from an address buffer;
- block selection decoding means for generating a block selection signal in response to an external address signal;
- and
- combining means for generating a normal block selection signal and a redundant block selection signal, said redundancy combining means comprising:
- means for generating said normal block selection signal in dependence upon the output of said redundant decoder and the block selection signal generated from said block selection decoder;
- and
- means for generating said redundant block selection signal in dependence upon the output of said redundant decoder and an inverted signal of the block selection signal generated from said block selection decoder.
A semiconductor memory device having a normal block and a redundant block, comprising:
- predecoding means for responding to external address signals by providing word line selection signals, local address signals, and redundant selection signals;
- first decoder means for responding to local address signals by providing normal block signals;
- second decoder means for responding to said redundant selection signals by providing redundant block signals unique to corresponding ones of a plurality of redundant blocks;
- combining means coupled for responding to said normal block signals and said redundant block signals, by providing either normal block selection signals or redundant block selection signals, in dependence upon logic states of said redundant block signals;
- and
- means for selecting word lines in a plurality of normal blocks of the memory device in dependence upon said word line selection signals and said normal block selection signals.
A semiconductor memory device, comprising:
- predecoding means for responding to external address signals by providing word line selection signals, local address signals and redundant selection signals;
- first decoder means for responding to local address signals by providing normal block signals;
- a plurality of first means for providing redundant block signals in response to corresponding intermediate selection signals;
- a plurality of second means for enabling application of said intermediate selection signals to corresponding ones of said first means in response to said redundant selection signals;
- means for controlling said application of said intermediate selection signals to said plurality of second means;
- combining means coupled for responding to said normal block signals and said redundant block signals, by providing either normal block selection signals or redundant block selection signals;
- and
- means for selecting word lines in a plurality of normal blocks of the memory device in dependence upon said word line selection signals and said normal block selection signals.
Dependencies are inferred from the claim text.