Semiconductor dies and wafers and methods for making

A semiconductor wafer comprising:

• a plurality of individual dies containing integrated circuits, the dies containing at least one signal node;
• scribe line area separating the dies to be severed through to cut the wafer into individual chips;
• integrated test circuitry formed within the scribe line area;
• and
• a conductive interconnecting line extending from the at least one signal node to the integrated test circuitry formed within the scribe line area.

A method of fabricating a semiconductor wafer comprising the following steps:

• processing a semiconductor wafer to form a plurality of individual dies containing integrated circuits and at least one signal node, the individual dies being formed on the wafer to define severing scribe line area between individual dies;
• forming at least one conductive interface test pad in the scribe line area;
• forming conductive interconnecting lines which extend from a plurality of signal nodes from different individual dies to the at least one conductive interface test pad in the scribe line area;
• testing individual dies in parallel by contacting a test probe with the at least one conductive interface test pad;
• designating which of the tested individual dies are defective;
• severing through the scribe line area, the conductive interface test pad, and interconnecting lines within the scribe line area, to form individual chips;
• and
• collecting operable chips.

A method of fabricating a semiconductor wafer comprising the following steps:

• processing a semiconductor wafer to form a plurality of individual dies containing integrated circuits and at least one signal node, the individual dies being formed on the wafer to define severing scribe line area between individual dies;
• forming integrated test circuitry within the scribe line area;
• forming conductive interconnecting lines which extend from a plurality of signal nodes from different individual dies to the integrated test circuitry within the scribe line area;
• testing individual dies by using the integrated test circuitry within the scribe line area;
• designating which of the tested individual dies are defective;
• severing through the scribe line area, the interconnecting lines within the scribe line area, and the integrated test circuitry within the scribe line area, to form individual chips;
• and
• collecting operable chips.