Normalizing pipelined floating point processing unit

A floating point processor for performing arithmetic operations on floating point numbers, comprising:

• a register file having at least two input registers and at least one output register, said input registers holding floating point numbers to be used as input operands in arithmetic operations and said output registers holding floating point numbers produced by said arithmetic operations;
• a floating point add unit having first and second inputs and an output, said add unit including means for denormalizing normalized numbers and means for normalizing denormalized numbers;
• a floating point multiply unit having first and second inputs and an output, said floating point multiply unit output being connected to at least one of said add unit inputs, said output of said add unit being connected to said first and second inputs of said multiply unit;
• a first input bus connecting a first one of said input registers to said first input of said add unit and said first input of said multiply unit;
• a second input bus connecting a second one of said input registers to said second input of said add unit and said second input of said multiply unit;
• and
• an output bus connecting said add unit output, said multiply unit output and said output register;
• wherein denormalized input operands provided to said multiply unit are propagated through said add unit for normalization and wherein normalized floating point numbers produced by said multiply unit are propagated through said add unit for denormalization.

A floating point processor for performing arithmetic operations on floating point numbers, comprising:

• a first input bus for transmitting a first series of floating point numbers to said floating point processor for arithmetic operations;
• a second input bus for transmitting a second series of floating point numbers to said floating point processor for arithmetic operations;
• an output bus for transmitting a third series of floating point numbers produced by arithmetic operations from said floating point processor;
• a floating point add unit having first and second inputs and an output, said add unit including means for denormalizing normalized numbers and means for normalizing denormalized numbers;
• a floating point multiply unit having first and second inputs and an output;
• a floating point divide unit having first and second inputs and an output;
• and
• a round unit for rounding floating point numbers, said round unit having an input and an output;
• wherein said first add unit input, said first multiply unit input and said first divide unit input are connected to said first input bus;
• said second add unit input, said second multiply unit input and said second divide unit input are connected to said second input bus;
• said add unit output is connected to said round unit input;
• said multiply unit output is connected to said round unit input and at least one of said add unit inputs;
• said divide unit output is connected to said round unit input and at least one of said add unit inputs;
• and
• said round unit output is connected to said first input bus, said second input bus and said output bus;
• wherein denormalized numbers included in said first series of floating point numbers transmitted to said multiply or divide units of said floating point processor are propagated through said add unit for normalization and wherein normalized numbers included in said third series of floating point numbers output by said mulitply or divide units are propagated through said add unit for denormalization.

In a floating point processor comprised of a first floating point arithmetic operation unit having means for normalizing denormalized numbers and means for denormalizing normalized numbers and a second arithmetic operation unit which operates on normalized floating point numbers, a method of pipelining floating point arithmetic operations comprising the steps of:

• providing first and second floating point numbers to said first and second arithmetic operation units;
• determining whether said first and second floating point numbers are denormalized;
• sequentially propagating said determined denormalized numbers through said first arithmetic operation unit for normalization while holding said normalized floating point numbers at the input of said second arithmetic operation unit;
• propagating said normalized floating point numbers through said second arithmetic unit for performing said second arithmetic operation;
• and
• providing a result of said second arithmetic operation as an output.