US 5,056,089 AGranted

Memory device

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsShigeru Furuta, Kenichi Takahira, Atsuo Yamaguchi, Takesi Inoue, Toshiyuki Matsubara, Shuzo Fujioka

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Abstract

A memory system storing data detects and corrects an error in the stored data. The memory device includes a coding circuit for generating a systematic code including a data word and an error checking and correcting (ECC) code when the data word is supplied from a data bus during data writing, a memory cell array for storing the systematic code, and a sense amplifier for reading the systematic code from the memory cell. An error checking and correcting system generates a syndrome from the systematic code, decodes the syndrome to determine whether an error exists, identifies a bit position at which an error has occurred, and corrects the error contained in the data word by inverting a bit of the data word in the position at which the error has occured. The system includes a multiplexer for outputting the corrected data word to the data bus and a code reading circuit, for example, an ECC code register, for reading the ECC code generated by the coding circuit directly into the data bus. With this arrangement, it is possible to immediately and independently check the function of the coding circuit without influence from the memory cell array.

Claims12

Dependent claims

A memory system for storing data and detecting and correcting an error in the stored data comprising:

an error checking and correcting (ECC) code generating circuit having an input connected to a data bus for generating an error checking and correcting code in response to a data word supplied from the data bus during data writing, said ECC code generating circuit having an output from which the ECC code is output, the data word and the ECC code together constituting a systematic code;
a memory device having a first input connected to the data bus to receive the data word and a second input connected to the output of said ECC code generating circuit for receiving and storing the systematic code and having an output;
an error detecting and correcting system connected to the output of said memory device for reading the systematic code, calculating a syndrome from the systematic code read from said memory device, decoding the syndrome to determine whether an error exists in a bit in the data word and to identify a bit position at which an error has occurred, and correcting the error contained in the data word by inverting the bit of the data word at the bit position at which the error was identified;
output means for outputting the corrected data word from the error detecting and correcting system to said data bus;
and
code reading means for reading out the ECC code generated by said ECC code generating circuit directly into said data bus whereby functional checking of said code generating circuit can be immediately performed without being influenced by said memory device.

3 more elements

A memory system for storing data received over a data bus and for detecting and correcting errors in the stored data comprising:

a first error checking and correcting (ECC) code generating circuit having an input connected to a data bus for receiving a data word to be stored and an output for outputting a first ECC code corresponding to the data word, the data word and the first ECC code together constituting a systematic code;
a memory device having a first input connected to the data bus to receive the data word and a second input connected to the output of said first ECC code generating circuit for receiving and storing the systematic code, said memory device having an output for outputting the stored systematic code;
a syndrome generating a circuit having an input connected to the output of said memory device for receiving the stored systematic code from said memory device and having an output for generating a syndrome which indicates whether an error is present in a bit in the stored data word and outputting the syndrome at the output;
a syndrome decoder having an input connected to the output of said syndrome generating circuit for receiving the syndrome and decoding the syndrome to identify a bit position of the data word at which an error has occurred and having an output for outputting a decoded word identifying the bit position at which an error was identified;
a bit correcting circuit having a first input connected to the output of said syndrome decoder for receiving the decoded word and a second input connected to the output of said memory device for receiving the stored data word and inverting the bit of the stored data word corresponding to the identified bit position, thereby correcting the error;
a multiplexer having a plurality of input including a first input connected to the output of said syndrome generating circuit and a second input connected to the output of said bit correcting circuit and having a first output of connected to the data bus for selectively enabling one of the first and second inputs to be output from said memory system;
and
means for outputting the first ECC code from the output of said first ECC code generating circuit to the data bus separately from the first ECC code of the systematic code stored in said memory device.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/306,565Filed 6 Feb 1989
Priority: JP 63-269038 Feb 1988
Granted: 8 Oct 1991
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 11/2215
Using arrangements specific to the hardware being tested: to test error correction or detection circuits
G06F 11/1008
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: in individual solid state devices
G06F 11/1076
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: parity data used in redundant arrays of…
G06F
Computing and data processing