Multiaccumulator sigma-delta fractional-N synthesis
AssigneeMotorola, Inc.
InventorsAlexander W. Hietala, Duane C. Rabe
Life of this patent
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Abstract
A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.
Claims41
A fractional-N synthesizer which divides a voltage controlled oscillator output signal frequency by a loop divider, the loop divider having a variable divisor controlled by a control input to create a feedback signal to be compared to a reference signal for frequency control of the voltage controlled oscillator, the fractional-N synthesizer comprising:
- means for accepting a first digital number presented as a first plurality of bits;
- means, including sigma-delta modulator means, for:
- (a) calculating an integral of a combination of a predetermined number of least significant bits of said first digital number and a control digital number, to produce a second digital number,
- (b) summing a predetermined number of most significant bits of said second digital number with said control digital number to produce a sum digital number, and
- (c) calculating an integral of a combination of a predetermined number of least significant bits of said second digital number and said sum digital number whereby a third digital number, related to a second integral of said first digital number, is produced;
- and
- means for selecting a predetermined number of most significant bits of said third digital number for coupling to the divisor control input of the loop divider and for coupling to said sigma-delta modulator means as said control digital number.
A fractional-N synthesizer which divides a voltage controlled oscillator output signal frequency by a loop divider, the loop divider having a variable divisor controlled by a control input to create a feedback signal to be compared to a reference signal for frequency control of the voltage controlled oscillator, the fractional-N synthesizer comprising:
- means for accepting a first digital number presented as a first plurality of bits;
- means for calculating a first integration of an addition of said first digital number and a predetermined number of most significant bits of a second digital number having a second plurality of bits, to create a third digital number comprising a third plurality of bits;
- means for calculating a second integration of an addition of a predetermined number of least significant bits of said third digital number and a summation of a predetermined number of most significant bits of said third digital number and said predetermined number of most significant bits of said second digital number, to create said second digital number;
- and
- means for selecting said predetermined number of most significant bits of said second digital number for coupling at least to the divisor control input of the loop divider.
A radio transceiver employing a fractional-N synthesizer to generate an operating frequency signal derived from a voltage controlled oscillator output signal, the fractional-N synthesizer dividing the voltage controlled oscillator output signal frequency by a loop divider, the loop divider having a variable divisor controlled by a control input to create a feedback signal to be compared to a reference signal for frequency control of the voltage controlled oscillator, the radio transceiver comprising:
- means for transmitting the operating frequency signal;
- means for accepting a first digital number presented as a first plurality of bits to determine, in part, the operating frequency signal;
- means, including sigma-delta modulator means, for:
- (a) calculating an integral of a combination of a predetermined number of least significant bits of said first digital number and a control digital number, to produce a second digital number,
- (b) summing a predetermined number of most significant bits of said second digital number with said control digital number to produce a sum digital number, and
- (c) calculating an integral of a combination of a predetermined number of least significant bits of said second digital number and said sum digital number whereby a third digital number, related to a second integral of said first digital number, is produced;
- and
- means for selecting a predetermined number of most significant bits of said third digital number for coupling to the divisor control input of the loop divider and for coupling to said sigma-delta modulator means as said control digital number.
A method of signal synthesis employing a fractional-N synthesizer which divides a voltage controlled oscillator output signal frequency by a loop divider, the loop divider having a variable divisor controlled by a control input to create a feedback signal to be compared to a reference signal for frequency control of the voltage controlled oscillator, the method comprising the steps of:
- accepting a first digital number presented as a first plurality of bits;
- calculating a first integration of an addition of said first digital number and a predetermined number of most significant bits of a second digital number having a second plurality of bits, to create a third digital number comprising a third plurality of bits;
- calculating a second integration of an addition of a predetermined number of least significant bits of said third digital number and a summation of a predetermined number of most significant bits of said third digital number and said predetermined number of most significant bits of said second digital number, to create said third digital number;
- and
- selecting said predetermined number of most significant bits of said third digital number for coupling at least to the divisor control input of the loop divider.
Dependencies are inferred from the claim text.