Basic cell for BiCMOS gate array
AssigneeSiArc
InventorAbbas El Gamel
Life of this patent
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Abstract
An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-channel transistor. Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor, a large N-channel pull-down transistor, and a small P-channel transistor. By using this cell, an extremely high compute capability per die area is achieved.
Claims30
A BiCMOS cell for use in a programmable gate array, said BiCMOS cell comprising:
- a plurality of P-channel transistors;
- a plurality of N-channel transistors;
- and
- one or more bipolar transistors, each of said one or more bipolar transistors sharing an N-well with one or more of said P-channel transistors so that said bipolar transistors may only be used as pull-up devices.
In a programmed BiCMOS gate array, one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices, wherein said pull-up devices are for driving an output of said one or more macrocells to a high state.
A BiCMOS cell for use in a programmable gate array, each cell comprising one or more substantially rectangular compute sections and one or more drive sections, each drive section comprising one or more bipolar transistors for use as pull-up devices in one or more macrocells, and one or more N-channel transistors for use as pull-down devices in said one or more macrocells for driving an output of said one or more macrocells to a low state, each compute section comprising components which may be interconnected to form a two-to-one multiplexer, said multiplexer having true and complement outputs, said true output being equal to a power supply voltage, said complement output being equal to ground potential.
A cell for use in a mask programmable gate array, said cell comprising:
- one or more substantially rectangular compute sections and one or more drive sections, each of said drive sections containing one or more MOS transistors which are substantially larger than MOS transistors within said compute sections, each compute section comprising:
- two or more sizes of P-channel transistors, where a size corresponds to a channel width;
- and
- two or more sizes of N-channel transistors,
- wherein said P-channel transistors comprise at least one medium size P-channel transistor and at least one small size P-channel transistor, wherein said small size P-channel transistor is smaller than said medium size P-channel transistor;
- and
- said N-channel transistor and at least one small size N-channel transistor and at least one medium size N-channel transistor, wherein said small size N-channel transistor has a greater current handling capability than said at least one medium size P-channel transistor, and wherein said medium size N-channel transistor is larger than said small size N-channel transistor.
An application Specific Integrated Circuit (ASIC), said ASIC comprising one or more arrays of BiCMOS cells and other circuitry for communicating with said arrays, said cells within said arrays of cells being programmed to form one or more logic circuit macrocells, said one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices.
Dependencies are inferred from the claim text.