Pipelined floating point processing unit

A pipelining floating point processor comprising:

• a floating point multiply unit having first and second inputs and an output;
• a floating point add unit having input means and an output;
• means for providing input operands to said multiply and add units;
• at least one accumulator for storing the results of arithmetic operations performed by said multiply and add units;
• means for providing the results stored in said at least one accumulator as accumulated operands to said multiply and add units;
• staging means for sequencing said input operands, results produced by said multiply and add unit using said input operands, and results produced by said mulitply and add units using said input operands and said accumulated operands, said staging means further comprising:
• means for temporarily delaying input operands to be provided to said multiply and add units for compound arithmetic operations while producing accumulated operands to be provided to said multiply and add units with said delayed input operands for compound arithmetic operations;
• a first latch connected to said output of said multiply unit, said first latch latching intermediate results produced by said multiply unit;
• and
• a second latch connected to said output of said floating point add unit, said second latch latching intermediate results produced by said add unit;
• said staging means providing for the pipelining of arithmetic operations, including compound arithmetic operations performed using said accumulated operands, through said floating point processor;
• and
• a denormalizer for denormalizing normalized numbers, said denormalizer having first and second inputs and input means;
• wherein the input means of said add unit is connected to said output means of said denormalizer.

A pipelining floating point processor comprising:

• a floating point multiply unit having first and second inputs and an output;
• a floating point add unit having first and second inputs and an output;
• means for providing input operands to said multiply and add units;
• at least one accumulator for storing the results of arithmetic operations performed by said multiply and add units;
• means for providing the results stored in said at least one accumulator as accumulated operands to said multiply and add units;
• staging means for sequencing said input operands, results produced by said multiply and add units using said input operands, and results produced by said multiply and add units using said input operands and said accumulated operands, said staging means further comprising:
• means for temporarily delaying input operands to be provide to said multiply and add units for compound arithmetic operations while producing accumulated operands to be provided to said multiply and add units with said delayed input operands for compound arithmetic operations;
• a first latch connected to said output of said multiply unit, said first latch latching intermediate results produced by said multiply unit;
• and
• a second latch connected to said output of said add unit, said second latch latching intermediate results produced by said add unit;
• wherein said staging means provides for the pipelining of arithmetic operations, including compound arithmetic operations performed using said accumulated operands, through said floating point processor;
• and
• a renormalizer for normalizing denormalized numbers, said renormalizer having an input connected to the output of said add unit and an ouput, wherein denormalized intermediate results produced by said add unit are input into said renormalizer for normalization.

A floating point processor comprising:

• a first arithmetic operation unit having a pair of inputs for receiving input operands and an output for transmitting a result of said first arithmetic operation;
• a second arithmetic operation unit having a pair of inputs for receiving input operands and an output for transmitting a result of said second arithmetic operation, said second arithmetic operation unit including a denormalizer for denormalizing normalized input operands;
• a renormalizer for normalizing denormalized results produced by said second arithmetic unit;
• a rounder unit having an input connected to said first arithmetic operation unit output, said second arithmetic operation unit output and said renormalizer output;
• at least one accumulator for storing the results of arithmetic operations performed by said first and second arithmetic operation unit, each of said at least one accumulators having an input and an output;
• means for providing said accumulator output to said first and second arithmetic operation units;
• and
• means for for pipelining input operands and results through said floating point processor.

A pipelining floating point processor comprising:

• at least one arithmetic operation unit, said at least one arithmetic operator unit including an adder having input and output means;
• means for providing input operands to said at least one arithmetic operation unit;
• at least one accumulator or storing the results of arithmetic operations performed by said at least one arithmetic operation unit;
• means for providing the results stored in said at least one accumulator as accumulated operands to said at least one arithmetic operation unit;
• a denormalizer for denormalizing normalized numbers, said denormalizer having input and output means, said input means of said add unit being connected to said output means of said denormalizer;
• staging means for sequencing said input operands, results produced by said at least one arithmetic operation unit using said input operands, and results produced by said at least one arithmetic operation unit using said input operands and said accumulated operands;
• wherein said staging means provides for the pipelining of arithmetic operations, including compound arithmetic operations performed using said accumulated operands, through said floating point processor.

A pipelining floating processor comprising:

• at least one arithmetic operation unit;
• means for providing input operands to said at least one arithmetic operation unit;
• at least one accumulator for storing the results of arithmetic operations performed by said at least one arithmetic operation unit;
• means for providing the results stored in said at least one accumulator as accumulated operands to said at least one arithmetic operation unit;
• a renormalizer for normalizing denormalized numbers, said renormalizer having an input connected to the output of said at least one arithmetic operation unit and an output, wherein denormalized intermediate results produced by said at least one arithmetic operation unit are input into said renormalizer for normalization;
• staging means for sequencing said input operands, results produced by said at least one arithmetic operation unit using said input operands, and results produced by said at least one arithmetic operation unit using said input operands and said accumulated operands;
• wherein said staging means provides for the pipelining of arithmetic operations, including compound arithmetic operations perfomed using said accumulated operands, through said floating point processor.