US 5,049,841 AGranted

Electronically reconfigurable digital pad attenuator using segmented field effect transistors

AssigneeGeneral Electric Company

InventorsPaul D. Cooper, Paul A. Bourdelais, Anthony W. Jacomb-Hood, John A. Windyka, David R. Helms, Ronald J. Naster

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Abstract

An electronically reconfigurable digital pad attenuator is disclosed using selectively controlled segmented field effect transistors in a passive, non-gain state as the principal impedance elements. The attenuator may be fabricated in the monolithic microwave integrated circuit (MMIC) format with a segmented gate field effect transistor being connected in each of the separate branches of a Pi pad, Tee pad, or Bridged Tee pad attenuator configuration. The individual FET segments are maintained in a high admittance "ON" state or a low admittance "OFF" state in accordance with the binary control potentials applied to the gate of each segment, the principal electrodes being maintained at a zero potential difference. The attenuation then becomes a function of the binary gate potentials applied to each segment and assumes one of a set of well-defined discrete values. The attenuator consumes minimum power, provides attenuation steps that are independent of GaAs MMIC fabrication process tolerances, i.e. lot to lot stable, is wide band, is well matched at input and output terminals, and facilitates setting nominal gain in microwave and millimeter wave subsystems while minimizing transmission phase variations without degrading dynamic range, extending dynamic range in communications receivers, and wide band accuracy in vector modulators.

Claims17

Dependent claims

An electronically reconfigurable Pi-pad attenuator providing a set of discrete attenuation states (S21 values) comprising

A) a monolithic crystalline substrate suitable for forming mutually insulated metallizations and field effect transistors,
B) a first metallization on said member forming a first note for application of an input signal and for internal signal connection,
C) a second metallization forming a second node for internal signal connection and for derivation of an output signal,
D) a third metallization forming a third node providing a common signal return for input, output and internal signals,
E) three segmented single gate field effect transistors (FETs) formed on said substrate, each subdivided into a first (m), second (n) and third (o) plurality of selectively controlled FET segments respectively, each segment having a predetermined width to achieve a desired admittance and including
(1) a first region having a first electrode in ohmic contact with said substrate,
L(2) a second region, spaced from the first region, having a second electrode in ohmic contact with said substrate, and
(3) a third region positioned between said first and second regions having a third electrode forming a gate for switching said segment to a high admittance "ON" state or to a low admittance "OFF" state in response to the state of a digital control potential,
each of said (m) segments being serially connected between said first and third metallizations in separate parallel paths,
each of said (n) segments being serially connected between said second and third metallizations in separate parallel paths,
each of said (o) segments being serially connected between said first and second metallizations in separate parallel paths,
F) means for maintaining said three metallizations at a common dc potential to facilitate passive, bidirectional conduction by the (m+n+o) segments of said three FETs with certain segments being in a high admittance "ON" state and other segments being in a low admittance "OFF" state in response to a binary control potential applied to the gate of each segment thereof, and
G) a plurality of control terminals for applying said binary control potential to the gate of each of said (m+n+o) segments, selected combinations of binary control potentials producing particular attenuation states for said attenuator.

10 more elements

An electronically reconfigurable Tee-pad attenuator providing a set of discrete attenuation states (S21 values), comprising

A) a monolithic crystalline substrate suitable for forming mutually insulated metallizations and field effect transistors,
B) a first metallization on said member forming a first node for application of an input signal,
C) a second metallization forming a second node for internal signal connection,
D) a third metallization forming a third node for derivation of an output signal,
E) a fourth metallization forming a fourth node providing a common signal return for input, output and internal signals,
F) three segmented single gate field effect transistors (FETs) formed on said member, each subdivided into a first (m), second (n) and third (o) plurality of selectively controlled FET segments, respectively, each segment having a predetermined width to achieve a desired admittance and including
(1) a first region having a first electrode in ohmic contact with said substrate,
(2) a second region, spaced from the first region, having a second electrode in ohmic contact with said substrate, and
L(3) a third region positioned between said first and second regions having a third electrode forming a gate for switching said segment to a high admittance "ON" state or to a low admittance "OFF" state in response to the state of a digital control potential,
each of said (m) segments being serially connected between said first and second metallizations in separate parallel paths,
each of said (n) segments being serially connected between said second and third metallizations in separate parallel paths, and
each of said (o) segments being serially connected between said second and fourth metallizations in separate parallel paths,
G) means for maintaining said four metallizations at a common dc potential to facilitate passive, bidirectional conduction by the (m+n+o) segments of said three FETs with certain segments being in a high admittance "ON" state and other segments being in a low admittance "OFF" state in response to a binary control potential applied to the gate of each segment thereof, and
H) a plurality of control terminals for applying said binary control potential to the gate of each of said (m+n+o) segments, selected combinations of binary control potentials producing particular attenuation states of said attenuator.

11 more elements

An electronically reconfigurable bridged Tee-pad attenuator providing a set of discrete attenuation states (S21 values), comprising

A) a monolithic crystalline substrate suitable for forming mutually insulated metallizations and field effect transistors,
B) a first metallization on said substrate forming a first node for application of an input signal,
C) a second metallization forming a second node for internal signal connection,
D) a third metallization forming a third node for derivation of an output signal,
E) a fourth metallization forming a fourth node providing a common signal return for input, output and internal signals,
F) two segmented single gate field effect transistors (FETs) formed on said substrate, each subdivided into a first (m) and second (n) plurality of selectively controlled FET segments, respectively, each segment having a predetermined width to achieve a desired admittance and including
(1) a first region having a first electrode in ohmic contact with said substrate,
(2) a second region, spaced from the first region, having a second electrode in ohmic contact with said substrate, and
(3) a third region positioned between said first and second regions having a third electrode forming a gate for switching said segment to a high admittance "ON" state or to a low admittance "OFF" state in response to the state of a digital control potential,
each of said (m) segments being serially connected between said first and third metallizations in separate parallel paths,
each of said (n) segments being serially connected between said second and fourth metallizations in separate parallel paths,
G) a first and a second resistor of equal values each having one terminal connected to said second metallization, the pair being serially connected between said first and third metallizations,
h) means for maintaining said two metallizations at a common dc potential to facilitate passive, bidirectional conduction by the (m+n) segments of said two FETs with certain segments being in a high admittance "ON" state and other segments being in a low admittance "OFF" state in response to a binary control potential applied to the gate of each segment thereof, and
I) an (m+n) fold plurality of control terminals for applying said binary control potential to the gate of each of said l(m+n) segments, selected combinations of binary control potentials producing particular attenuation states for said attenuator.

11 more elements

Dependencies are inferred from the claim text.