US 5,049,766 AGranted

Delay measuring circuit

AssigneeNCR Corporation

InventorsHans van Driest, Hendrik van Bokhorst, Richard Kruithof

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Abstract

In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter (22) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-l to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.

Claims9

Dependent claims

A delay measuring circuit, comprising:

input means adapted to receive an applied clock signal;
a switching device having an intrinsic delay and having a plurality of inputs and a plurality of control inputs;
a delay line coupled to said input means, having a plurality of individual delay cells with outputs thereof respectively connected to certain of said inputs of said switching device;
counter means having an input coupled to said input means and having output means coupled to certain of said plurality of control inputs of said switching device to thereby connect a selected input of said switching device to an output thereof;
latch means coupled to said output means of said counter means for latching a count value in said counter means;
a delay device having a delay substantially equal to the intrinsic delay of said switching device and being coupled to said input device;
and
phase comparator means having inputs coupled to an output of said switching device and to an output of said delay device, and having output means coupled to said counter means and to said latch means,
whereby in response to a phase comparison match, a count value in said counter means is latched into said latch means and said counter means is reset to a predetermined value, such that said latch means stores a value dependent on the delay of one of the individual delay cells.

6 more elements

A timing monitoring circuit, comprising:

input means adapted to receive an applied clock signal;
a switching device having an intrinsic delay and having a plurality of inputs and a plurality of control inputs;
a delay line coupled to said input means, having a plurality of individual delay cells with outputs thereof respectively connected to certain of said inputs of said switching device;
counter means having an input coupled to said input means and having output means coupled to certain of said plurality of control inputs of said switching device to thereby connect a selected input of said switching device to an output thereof;
latch means coupled to said output means of said counter means for latching a count value in said counter means;
a delay device having a delay substantially equal to the intrinsic delay of said switching device and being coupled to said input device;
phase comparator means having inputs coupled to an output of said switching device and to an output of said delay device, and having output means coupled to said counter means and to said latch means, whereby in response to a phase comparison match, a count value in said counter means is latched into said latch means and said counter means is reset to a predetermined value, such that said latch means stores a value dependent on the delay of one of the individual delay cells;
additional input means adapted to receive a predetermined maximum value;
and
comparator means having an output, a first input coupled to said output of said latch means and a second input coupled to said additional input means to receive said predetermined maximum value, whereby said comparator means provides an output signal in response to the value stored in said latch means exceeding said predetermined maximum value.

7 more elements

A delay control circuit, comprising:

input means adapted to receive an applied clock signal;
a switching device having an intrinsic delay and having a plurality of inputs and a plurality of control inputs;
a delay line coupled to said input means, having a plurality of individual delay cells with outputs thereof respectively connected to certain of said inputs of said switching device;
counter means having an input coupled to said input means and having output means coupled to said latch means and to certain of said plurality of inputs of said switching device to thereby connect a selected input of said switching device to an output thereof;
latch means coupled to said output means of said counter means for latching a count value in said counter means;
a delay device having a delay substantially equal to the intrinsic delay of said switching device and being coupled to said input device;
phase comparator means having inputs coupled to an output of said switching device and to an output of said delay device, and having output means coupled to said counter means an to said latch means whereby in response to phase comparison match, a count value in said counter means is latched into said latch means and said counter means is reset to a predetermined value, such that said latch means stores a value dependent on the delay of one of the individual delay cells;
signal input means adapted to receive a signal to be delayed;
a further delay line coupled to said signal input means and having a plurality of individual delay cells;
signal output means;
and
selection means coupled to said latch means and to said further delay line, said selection means having an input and being adapted to select the output of one of said individual delay cells of said further delay line for connection to said signal output means, independence upon a control signal applied to said input of said selection means, whereby a signal applied to said signal input means is delayed by a fraction of the period of said applied clock signal, corresponding to said control signal, the delayed input signal being provided as an output signal on aid signal output means.

9 more elements

Dependencies are inferred from the claim text.