Digital error correction system for subranging analog-to-digital converters

A multi-stage, pipelined subranging analog-to-digital converter, comprising:

• a plurality of cascade-coupled conversion stages, each of said stages including first means responsive to an analog input signal for generating a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, second means responsive to said binary conversion signal for generating a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, third means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, and a look-up table for generating a compensated binary signal selected by said binary conversion signal, said look-up table including a number of binary address inputs equal to the number n.sub.i of bits of said first means in said each conversion stage, said binary word size of each coefficient in said look-up table being greater than the total number of bits n.sub.i of said first means in said each conversion stage to facilitate correction and calibration of said analog-to-digital converter;
• a separate interstage amplifier located, respectively, between each set of successive conversion stages, respectively, the gain of each of said amplifiers being less than 2.sup.ni where n.sub.i is the number of bits in the binary conversion signal of each stage preceding a respective one of said amplifiers;
• and
• means for combining said compensated binary signals from said look-up tables into a binary output signal.

A multi-stage, pipelined subranging analog-to-digital converter comprising:

• a plurality of cascade-coupled conversion stages, each of said stages including first means responsive to an analog input signal for generating a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, second means responsive to said binary conversion signal for generating a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, and third means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage;
• a common look-up table for at least a predetermined number of most significant bit conversion stages for generating a compensated binary signal selected by said binary conversion signals of said most significant bit stages;
• a separate look-up table for each respective one of the conversion stages not included within said predetermined number, for generating a compensated binary signal selected by said binary conversion signal of each respective one of said conversion stages not included within said predetermined number;
• and
• means for combining said compensated binary signals from said common look-up table and said separate look-up tables into a binary output signal.

A multi-stage, pipelined subranging analog-to-digital converter, comprising:

• a plurality of cascade-coupled conversion stages, each of said stages including an analog-to-digital converter for converting an analog input signal into a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting said binary conversion signal into a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, summation means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, an interstage amplifier coupling said each of said stages to the next successive conversion stage, the gain of said amplifier being less than 2.sup.ni where n.sub. is the number of bits in the binary conversion signal of said each of said stages, and a look-up table for generating a compensated binary signal selected by said binary conversion signal, said look-up table having n.sub.i binary address inputs and 2.sup.ni coefficients and
• wherein, in said each conversion stage, binary word size of each coefficient in said look-up table is greater than the total number of bits n.sub.i of the analog-to-digital converter therein to facilitate correction and calibration of said multi-stage, pipelined subranging analog-to-digital converter;
• and
• means for combining said compensated binary signals from the look-up tables into a binary output signal.

A multi-stage, pipelined subranging analog-to-digital converter comprising:

• a plurality of cascade-coupled conversion stages, each of said stages including an analog-to-digital converter for converting an analog input signal into a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting said binary conversion signal into a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, summation means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, an interstage amplifier coupling said each of said stages to the next successive conversion stage, the gain of said amplifier being less than 2.sup.ni where n.sub.i is the number of bits in the binary conversion signal of said each of said stages;
• a plurality of look-up tables for generating a compensated binary signal selected by said binary conversion signal, a first of said look-up tables being coupled to a plurality of said stages producing the most significant bits, and at least a separate look-up table being coupled to the stage producing the least significant bit;
• and
• means for combining said compensated binary signals from the look-up tables into a binary output signal.

A digital calibration system for a multi-stage, pipelined subranging analog-to-digital converter, said converter including a plurality of cascade-coupled conversion stages, each of said stages including an analog-to-digital conversion signal corresponding to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting said binary conversion signal into a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, summation means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, and a look-up table for generating a compensated binary signal selected by said binary conversion signal, said converter further including means for combining the compensated binary signals from the look-up tables in each of said stages into a binary output signal, said digital calibration system comprising:

• a plurality of calibration look-up tables corresponding, respectively, to the look-up tables of the analog-to-digital converter conversion stages;
• means for applying an analog input signal to the multi-stage analog-to-digital converter;
• means for applying the binary conversion signals from the analog-to-digital converters of said conversion stages to said calibration look-up tables;
• means for combining the compensated binary signals from said calibration look-up tables into a binary calibration signal;
• means for comparing the binary calibration signal with another binary signal corresponding to the analog input signal applied to the multi-stage analog-to-digital converter, to produce an error signal;
• and
• means responsive to the error signal for correcting the compensated binary signals stored in said calibration look-up tables.

A digital calibration system for a multi-stage, pipelined subranging analog-to-digital converter, said converter including a plurality of cascade-coupled conversion stages, each of said stages including an analog-to-digital converter for converting an analog input signal into a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting said binary conversion signal into a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, and summation means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, said converter further including a plurality of look-up tables for generating a compensated binary signal selected by those of the binary conversion signals respectively supplied thereto, and means for combining the compensated binary signals from the look-up tables into a binary output signal, said digital calibration system comprising:

• a plurality of calibration look-up tables corresponding, respectively, to the look-up tables of the analog-to-digital converter;
• means for applying an analog input signal to the multi-stage analog-to-digital converter;
• means for applying the binary conversion signals from the analog-to-digital converters of said conversion stages to said calibration look-up tables;
• means for combining the compensated binary signals from said calibration look-up tables into a binary calibration signal;
• means for comparing the binary calibration signal with another binary signal corresponding to the analog input signal applied to the multi-stage analog-to-digital converter, to produce an error signal;
• and
• means responsive to the error signal for correcting the compensated binary signals stored in said calibration look-up tables.