A field effect transistor differential amplifier having first and second input terminals and first and second output terminals, comprising in combination:
- (a) a first stage including first and second input field effect transistors, first and second cascode field effect transistors, a first current source field effect transistor, and first and second load devices, the first current source field effect transistor having a drain coupled to a source of each of the first and second input field effect transistors, the first input field effect transistor having its gate coupled to the first input terminal and a drain coupled to a source of the first cascode field effect transistor, the first cascode field effect transistor having a gate connected to a first reference voltage conductor and a drain coupled by a first conductor to a first terminal of the first load, device, a second terminal of the first load device being coupled to a first supply voltage conductor, the second input field effect transistor having a gate coupled to the second input terminal and a drain coupled to a source of the second cascode field effect transistor, the second cascode field effect transistor having a drain coupled by a second conductor to a first terminal of the second load device and a gate coupled to the gate of the first cascode transistor, a second terminal of the second load device being coupled to the first supply voltage conductor;
- (b) a second state including third and fourth input field effect transistors having gates coupled to the first and second conductors, respectively, a second current source field effect transistor, and third and fourth load devices, the second, current source field effect transistor having a gate and source coupled to a gate and source, respectively, of the first current source field effect transistor, and a drain coupled to a source of each of the third and fourth input field effect transistors, the third input field effect transistor having a drain coupled by a third conductor to a first terminal of the third load device, the third load device having a second terminal coupled to the first supply voltage conductor, a drain of the fourth input field effect transistor being coupled by a fourth conductor to a first terminal of the fourth load device, a second terminal of the fourth load device being coupled to the first supply voltage conductor;
- (c) a first capacitor having a first terminal coupled to the third conductor and a second terminal coupled to a fifth conductor, and a second capacitor having a first terminal coupled to the fourth conductor and a second terminal coupled to a sixth conductor;
- (d) a first auto-zeroing field effect transistor having a source coupled to the fifth conductor, a gate coupled to receive an auto-zeroing control signal, and a drain coupled to a second reference voltage conductor, and a second auto-zeroing field effect transistor having a source coupled to the sixth conductor, a gate coupled to receive the auto-zeroing control signal, and a drain coupled to the second reference voltage conductor;
- (e) a third cascode field effect transistor having a source coupled to the drain of the first current source transistor, a gate coupled to a third reference voltage conductor, and a drain coupled to the sources of the first and second input field effect transistors;
- (f) a fourth cascode field effect transistor having a source coupled to the drain of the second current mirror field effect transistor, and a drain coupled to the sources of the third and fourth input field effect transistors;
- wherein the fifth and sixth conductors are connected to the inputs of a third stage similar to the second stage, and a pair of complementary output conductors of the third stage are coupled to inputs of a fourth stage similar to the second stage, the fourth stage having a pair of complementary output conductors connected to first terminals of third and fourth capacitors, respectively, the field effect transistor differential amplifier including third and fourth auto-zeroing field effect transistors having source electrodes connected to second terminals of the third and fourth auto-zeroing capacitors, respectively, the third and fourth auto-zeroing field effect transistors having gate electrodes coupled to receive the auto-zeroing control signal and each having a drain coupled to the second reference voltage conductor, the second terminals of the third and fourth capacitors being coupled to a pair of differential inputs of a field effect transistor latch, whereby the field effect transistor differential amplifier in combination with the field effect transistor latch form a comparator.