US 5,047,360 AGranted

Method of manufacture thin film transistors

AssigneeU.S. Philips Corporation

InventorKeith H. Nicholas

Life of this patent

Estimating the term…

Loading patent…

Abstract

A TFT is fabricated by providing on a substrate (10), and over a gate (12), a sequentially formed multi-layer structure consisting of a gate insulator layer (14), an intrinsic semiconductor, e.g. a-Si or polysilicon, layer (16) for the channel, a doped semiconductor, e.g. n type a-Si or polysilicon, layer (18) for source and drain contact regions and a passivating layer (20). The layer (18) extends completely over and covers the channel region of the layer (16). Thereafter, the portion (30) of layer (18) overlying the channel region is converted by a compensating doping implant to a highly resistive form separating the source and drain contact regions, and windows (22, 24) are defined in the passivating layer (20) into which source and drain contacts (26, 28) are deposited. In this way critical interfaces are protected from contamination. The TFT is suitable for use as a switching element in active matrix display devices, e.g. LC-TVs.

Claims5

Dependent claims

A method of fabricating a TFT comprising the steps of

(a) forming a gate electrode on a substrate;
(b) forming a multi-layer structure over said gate electrode on said substrate, said multi-layer structure including in superimposed relationship:
a gate insulator layer,
an intrinsic semiconductor layer providing a channel region,
a doped semiconductor layer extending over said channel region, and
a passivating layer;
(c) forming windows in said passivating layer to expose respective underlying areas of said doped semiconductor layer, said windows being above said doped semiconductor layer at respective sides of said gate electrode;
(d) depositing contact material into said windows to form source and drain contacts, and
(e) implanting further dopants into said doped semiconductor layer through said passivating material by using said contact material in said windows as a mask, said further dopants converting said doped semiconductor layer between said contact material into a high resistance region, said high resistance region being above said gate electrode.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/390,850Filed 8 Aug 1989
Priority: GB 882296030 Sep 1988
Granted: 10 Sep 1991
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 30/0316
Characterised by the gate electrodes: of lateral bottom-gate TFTs comprising only a single gate
G02F 1/1368
Active matrix addressed cells: in which the switching element is a three-electrode device
H10D 30/0321
Of thin-film transistors [TFT]: comprising silicon, e.g. amorphous silicon or polysilicon
H10D 30/6732
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: bottom-gate only TFTs