Single anneal step process for forming titanium silicide on semiconductor wafer

An improved process for forming titanium silicide on a silicon semiconductor wafer using a single annealing step at first and second temperature without an intervening etching step which comprises:

• a) providing a silicon semiconductor wafer having one or more silicon surface regions on which said titanium silicide is to be formed;
• b) cleaning said wafer in a sealed cleaning chamber using an rf plasma and a gaseous mixture which includes at least one reactive gas;
• c) transferring the cleaned wafer to a vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said cleaning chamber;
• d) forming a titanium layer over said cleaned wafer in said vacuum deposition chamber in the substantial absence of oxygen-bearing gases;
• e) transferring the titanium coated wafer to an annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber;
• and
• f) annealing the titanium-coated silicon semiconductor wafer in a nitrogen-bearing atmosphere in said annealing chamber, and in the substantial absence of oxygen-bearing gases, by initially heating said wafer to a first temperature ranging from about 500.degree. up to about 695.degree. C. for a time period ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 5.degree./second to about 150.degree. C./second to form titanium silicide, and to form titanium nitride over said titanium silicide and over silicon oxide (SiO.sub.2) surfaces on said wafer, and then, without removing the wafer from said annealing chamber, further annealing said wafer at a second temperature ranging from about 800.degree. to about 900.degree. C. for an additional time period ranging from about 20 to about 60 seconds to convert said titanium silicide to a stable phase.

An improved process for forming titanium silicide on a silicon semiconductor wafer using a single annealing step at first and second temperature without an intervening etching step which comprises:

• a) providing a silicon semiconductor wafer having one or more silicon surface regions on which said titanium silicide is to be formed;
• b) cleaning said wafer in a sealed cleaning chamber using an rf plasma and a gaseous mixture containing at least one reactive gas;
• c) transferring the cleaned wafer to a vacuum deposition chamber without substantially exposing said cleaned wafer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said cleaning chamber;
• d) forming a titanium layer over said cleaned wafer in said vacuum deposition chamber in the substantial absence of oxygen-bearing gases;
• e) transferring the titanium coated wafer to an annealing chamber without substantially exposing the newly formed titanium layer to oxygen-bearing gases by transferring said wafer through a sealed central chamber which is interconnected to both said vacuum deposition chamber and said sealed annealing chamber;
• f) annealing the titanium-coated silicon semiconductor wafer in a nitrogen-bearing atmosphere in said annealing chamber, and in the substantial absence of oxygen-bearing gases, at a first temperature ranging from about 600.degree. to about 675.degree. C. for a period of time ranging from about 20 seconds to about 60 seconds by raising the temperature of said wafer at a rate within a range of from about 520 /second to about 150.degree. C./second to form said titanium silicide, as well as to form titanium nitride over said titanium silicide which inhibits migration of underlying silicon to the surface, and to react substantially all of the titanium overlying silicon oxide (SiO.sub.2) regions on said wafer to form titanium nitride, whereby subsequent annealing of said wafer at a higher temperature will not result in reaction between said silicon oxide and unreacted titanium overlying said silicon oxide;
• and
• g) then, without removing the wafer from said annealing chamber, raising the wafer temperature at a rate within a range of from about 5.degree./second to about 150.degree. C./second to a second temperature ranging from about 800.degree. to about 900.degree. C. to further anneal said wafer for an additional time period ranging from about 20 to about 60 seconds to convert said titanium silicide into a stable phase.