Phase comparison circuit

A phase comparison circuit, particularly for a phase-locked loop (PLL) in a decoder for multiplex signals, comprising a double balanced mixer stage which receives a sine signal, particularly the pilot of a multiplex signal, as well as said sine signal in anti-phase and a square-wave switching signal of the same switching frequency, which switching signal is derived particularly from the frequency of a phase-locked loop, characterized in that two active current mirror circuits are provided whose outputs supply the phase comparison signal and in which at least two common negative feedback circuit elements (24, 25) are arranged, the first element (24) being operative in the input-sided negative feedback of the first current mirror circuit and in the output-sided negative feedback of the second current mirror circuit, and the second element (25) being operative in the output-sided negative feedback of the first current mirror circuit and in the input-sided negative feedback of the second current mirror circuit, and in that the two current mirror circuits are alternately connected to the two balanced mixer stages by means of a switching stage during the half cycle clock of the switching signal.