CMOS clock-phase synthesizer

An integrated circuit for changing the phase relationship between at least two clock-phase outputs and a reference clock, said clock-phase outputs being generated by a digital waveform synthesizer including a synchronous delay line (SDL) coupled to at least two digital-to-time domain converters (DTCs), said SDL generating N taps, said taps corresponding to the resolution of said clock-phase outputs said DTCs outputting said clock-phase outputs, said DTCs being further coupled to a pattern register, said pattern register being coupled to a pattern generator, said integrated circuit comprising:

• a sequence control coupled to said reference clock over a clock buffer for receiving a plurality of frequencies therefrom, said sequence control being further coupled to said SDL for generating a plurality of global signals for triggering said digital waveform synthesizer, said sequence control being coupled to said pattern generator for synthesizing a plurality of clock-phase waveforms;
• at least one shifter coupled to said pattern register for minimizing the delays of said clock-phase outputs with respect to said reference clock, said shifter being coupled to said pattern generator for receiving a plurality of pattern bits therefrom, said plurality of pattern bits representing said plurality of clock-phase waveforms;
• and
• a deskew control being coupled to one of said clock-phase outputs and to said reference clock for determining the skew between said one of said clock-phase outputs and said reference clock, said deskew control being further coupled to said shifter for generating a plurality of control signals for minimizing the skew between said clock-phase outputs and said reference clock, said deskew control being further coupled to said pattern generator and to said sequence control for stretching the clock cycles of said clock-phase outputs in debugging the logic path of any integrated circuit.