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US 5,034,685 AGranted
Test device for testing integrated circuits
OwnerGlenn J. Leedyinventor
Life of this patent
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OwnerGlenn J. Leedyinventor
Estimating the term…
Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of CAD. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surface traces are then connected, by means of multiplexers, to a conventional tester signal processor.
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:
A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:
Dependencies are inferred from the claim text.