Sense amplifier with an integral logic function

In a data processor having means for storing data, a circuit comprising:

• first and second input transistors respectively having first current electrodes coupled to a virtual ground node, and respectively receiving first and second signals on control electrodes thereof;
• a third transistor having a first current electrode coupled to a second current electrode of said first transistor, a control electrode, and a second current electrode coupled to a positive power supply voltage terminal;
• a fourth transistor having a first current electrode coupled to a second current electrode of said second transistor, a control electrode coupled to said control electrode of said third transistor, and a second current electrode coupled to said positive power supply voltage terminal;
• and
• logic means coupled to said first, second, third, and fourth transistors, for coupling together said control electrode and said first current electrode of said third transistor in response to a complement of a control signal, and for coupling together said control electrode and said first current electrode of said fourth transistor in response to said control signal.

In a data processor having means for storing data, a method of simultaneously performing a logic function and a compare operation in a single circuit comprising the steps of:

• enabling the circuit for operation;
• making conductive either a first input transistor receiving a first input signal, or a a second input transistor receiving a second input signal, first current electrodes of said first and second transistors each coupled to a negative power supply voltage terminal when the circuit is enabled;
• selectively coupling second current electrodes of said first and second input transistors substantially to a positive power supply voltage terminal in response to first and second control signals, respectively;
• and
• providing an output signal either in response to a difference between said first input signal and said second input signal if said first control signal assumes a predetermined logic state, or in response to a difference between said second input signal and said first input signal if said second control signal assumes said predetermined logic state.