Memory selftest method and apparatus same

A method for testing a memory device, said memory device comprising a plurality of memory locations each having a corresponding memory address, said method comprising the steps of:

• (a) generating each of said memory addresses in a predetermined order;
• (b) generating a predetermined series of data words;
• (c) storing one of said data words at each memory location corresponding to the memory addresses generated in step (a);
• (d) reading each data word stored in step (c);
• (e) regenerating said predetermined series of data words generated in step (b);
• (f) comparing each data word read in step (d) with a corresponding data word regenerated in step (e);
• (g) generating an error signal for each comparison performed in step (f) if the compared data words are not equivalent;
• and
• (h) utilizing said error signals generated in step (g) to store a portion of the memory address of each data word read in step (d) that is not equivalent to the corresponding data word generated in step (e), said portion being stored as a single bit in an accumulating register.

A method for testing a memory device, said memory device comprising a plurality of memory locations each having a corresponding memory address, said method comprising the steps of:

• (a) generating each of said memory addresses in a predetermined order;
• (b) generating a predetermined series of data words;
• (c) storing one of said data words at each of said memory locations;
• (d) regenerating said predetermined series of data words;
• (e) reading each data word stored in step (c);
• (f) comparing each data word regenerated in step (d) with a corresponding data word read in step (e) and, for each comparison:
• (i) if the compared data words are equivalent, inverting one of the data words and storing the inverted data word in the memory location in which said read data word was located;
• or
• (ii) if the compared data words are not equivalent, storing one of said compared data words in the memory location in which said read data word was located and generating an error status signal;
• (g) reading each data word stored in memory in step (f);
• (h) generating a second series of data words each of which is the inverse to the corresponding data word in said predetermined series of data words;
• (i) comparing each data word read from memory in step (g) with the corresponding data word generated in step (h);
• and
• (j) generating an error status signal for each comparison performed in step (i) if the compared data words are not equivalent.

A linear feedback shift register for generating a pseudo-random series of digital numbers, said linear feedback shift register comprising:

• a plurality of stages, each stage storing either a zero or a one and each stage having an output determined by its stored digital value;
• a feedback path connecting one or more of said outputs to an input of one of said stages;
• a decoder for receiving a plurality of said outputs of said stages and determining when each of said received outputs has a first predetermined value or a second predetermined value;
• zero generating means for generating a zero in each of said plurality of stages in response to said decoder detecting the existence of said first predetermined value such that each of said outputs is a zero;
• and
• means for generating a one in at least one of said stages in response to said decoder detecting the existence of said second predetermined value.

A linear feedback shift register for generating a pseudo-random series of digital numbers, said linear feedback shift register comprising:

• a plurality of stages, each stage storing either a zero or a one and each stage having an output determined by its stored digital value;
• first and second feedback paths and connection means for connecting either said first feedback path or said second feedback path to one of said stages,
• a decoder for receiving a plurality of said outputs of said stages and determining when each of said received outputs has a predetermined value;
• and
• zero generating means for generating a zero in each of said plurality of stages in response to said decoder detecting the existence of said predetermined value such that each of said outputs is a zero.

In a computer storage system having a memory device comprising a plurality of sections, each of said sections comprising a plurality of memory storage locations, a device for indicating which of said sections of memory has a malfunctioning memory storage location, said device comprising:

• testing means for testing each of said memory storage locations to determine which of said memory storage locations are malfunctioning,
• a decoder for receiving the memory address of each memory storage location determined to be malfunctioning by said testing means and, for each received address, outputting a signal indicating which of said plurality of sections contains the memory storage location corresponding to said received address;
• and
• a storage device for storing the outputs of said decoder.