Double rate oversampled interpolative modulators for analog-to-digital conversion

A double-rate second-order oversampled interpolative modulator for analog-to-digital conversion comprising:

• first and second switched capacitor integrators each having at least one input and at least one output, an input of said second switched capacitor integrator being coupled to an output of said first switched capacitor integrator;
• L-bit analog-to-digital conversion means coupled to the output of said second switched capacitor integrator for generating an L-bit digital output signal;
• and
• L-bit digital-to-analog conversion means coupled to receive said L-bit digital output signal of said L-bit analog-to-digital conversion means and to generate a quantized analog voltage proportional to said L-bit digital output signal, wherein L is the quantization level of said analog-to-digital and digital-to-analog conversion means, each of said first and second switched capacitor integrators includes an operational amplifier, a feedback capacitor, and sampling means, respectively, and each said sampling means comprises:
• first and second switch means for alternately sampling an input signal and said quantized analog voltage proportional to said L-bit digital output signal,
• first and second input capacitors adapted to be alternately charged by said input signal and said quantized analog voltage, and
• third and fourth switch means for alternately coupling said first and second capacitors to ground and to an input of said operational amplifier,
• said switch means being operable by predetermined phases of a clock in order to enable the integrator that includes said each sampling means to perform an integration twice per clock cycle so as to double an effective operating rate of the oversampled modulator.

A double-rate third-order oversampled interpolative modulator for analog-to-digital conversion comprising:

• first, second and third switched capacitor integrators each having at least one input and at least one output, an input of said second switched capacitor integrator being coupled to an output of said first switched capacitor integrator and an input of said third switched capacitor integrator being coupled to an output of said second switched capacitor integrator;
• L-bit analog-to-digital conversion means coupled to the output of said second switched capacitor integrator for generating an L-bit digital output signal;
• L-bit digital-to-analog conversion means coupled to receive said L-bit digital output signal of said L-bit analog-to-digital conversion means and to generate a first quantized analog voltage proportional to said L-bit digital output signal;
• M-bit analog-to-digital conversion means coupled to the output of said third switched capacitor integrator for generating an M-bit digital output signal;
• M-bit digital-to-analog conversion means coupled to receive said M-bit digital output signal of said M-bit analog-to-digital conversion means and to generate a second quantized analog voltage proportional to said M-bit digital output signal, wherein L and M each represents a quantization level of said L-bit analog-to-digital and digital-to-analog conversion means and said M-bit analog-to-digital and digital-to-analog conversion means, respectively, each of said first, second and third switched capacitor integrators includes an operational amplifier, a feedback capacitor, and sampling means, respectively, and each said sampling means comprises:
• first and second switch means for alternately sampling an input signal and said first quantized analog voltage, said first and second switch means of said first and second switched capacitor integrators being coupled to sample said first quantized analog voltage and said first and second switch means for said third switched capacitor integrator being coupled to sample said second quantized analog voltage,
• first and second input capacitors for being charged alternately by said input signal and said first quantized analog voltage, and
• third and fourth switch means for alternately coupling said first and second capacitors to ground and to an input of said operational amplifier of said first and second switched capacitor integrators, respectively, each of said switch means being operated by a predetermined clock phase, respectively, to enable said switched capacitor integrator in which it is included to perform an integration twice per clock cycle so as to double an effective operating rate of the oversampled modulator;
• and
• digital canceler means coupled to receive output signals from said second and third switched capacitor integrators for providing an output signal from said modulator.