Multiplexed encoder and decoder with address mark generation/check and precompensation circuits
AssigneeIndustrial Technology Research Institute
InventorPo C. Huang
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AssigneeIndustrial Technology Research Institute
InventorPo C. Huang
Estimating the term…
A two-level multiplexed encoder/decoder based on a novel technique of code table compression is disclosed. By means of comparing various code conversion tables such as well-known tables for use in NRZ-MRM, NRZ-RLL conversion schemes, separate code word condition sets are obtained. In accordance with the code word condition sets thus obtained, a two-level multiplexed encode and decode logic can be easily constructed. The code word condition sets representing the compressed code relations are sensed in the first level and are used further to set up the operation of a connected network of a multiplexed logic circuit in the second level. The AM generation/check and precompensation circuit necessary for the encoder and decoder are incorporated as an integral part. This method is applicable when more than two code tables are needed to be integrated in a single encoder/decoder.
An encoder/decoder apparatus for encoding data which is to be encoded prior to insertion in a channel and for decoding encoded data received from said channel, said apparatus comprising:
A method for encoding data which is to be transmitted through a channel, comprising:
Dependencies are inferred from the claim text.