Multiplexer circuit
AssigneeXAAR Limited
InventorW. Scott Bartky
Life of this patent
Estimating the term…
Loading patent…
AssigneeXAAR Limited
InventorW. Scott Bartky
Estimating the term…
A multiplexer circuit for effecting, in successive phases of operation, actuation of selected ones of respective groups of a plurality of capacitance actuated devices electrically represented by a plurality of series-connected capacitors, each device corresponding to an adjacent pair of the capacitors. The multiplexer includes a signal generator and a plurality of parallel electrical paths connected thereacrosss. Each path includes the common node formed by the capacitor pair corresponding to a respective one of the devices and first and second switches. A logic circuit is initially operable for respectively closing and opening the first and second switches of a selected path in one group and respectively opening and closing the first and second switches of the paths adjacent thereto for charging the two capacitors connected to the selected path. The logic circuit is subsequently operable for respectively opening and closing the first second switches of the selected path for discharging the two capacitors to effect actuation of the device corresponding to the charged and discharged capacitors. The voltage level of which the capacitors are charged is controlled based upon the operational status of adjacent devices of the same group.
A multiplexer circuit for effecting, in successive phases of operation, actuation of selected capacitance actuated devices arranged in respective groups, said devices being represented by a plurality of series-connected capacitors with each device corresponding to a pair of successive capacitors, each of said successive capacitor pairs defining a common node therebetween, comprising:
A multiplexer circuit for effecting, in successive phases of operation, actuation of selected capacitance actuated devices arranged in respective groups, said devices being represented by a plurality of series-connected capacitors with each device corresponding to an adjacent pair of said capacitors, each of said adjacent capacitor pairs defining a common node therebetween, comprising:
Dependencies are inferred from the claim text.