US 5,027,007 A · FFL/QFL FET logic circuits

Abstract

An FFL/QFL family of logic gates is disclosed, preferably implemented with GaAs MESFET devices and providing enhanced speed-power characteristics. Although a number of gate configurations are disclosed, a NOR gate 26 constructed in accordance with this invention includes a pair of normally OFF input transistors Q1 and Q7, which receive inputs A and B. Current sources Q2 and Q3 couple the transistors to the supply voltage V.sub.DD and ground, respectively. A control transistor Q6 is also coupled to the input and source transistors. An output section 30 responds to the combined operation of transistors Q1, Q2, Q3, Q6, and Q7 to produce an output C in accordance with conventional NOR logic. More particularly, upon application of a high logic input A or B to transistors Q1 and/or Q7, transistors Q1 and/or Q7 and Q6 turn ON and the output C is at a logic low level. If both inputs A and B are low, however, transistors Q1, Q6, and Q7 remain OFF, and the output C is at a high logic level. Use of the control transistor Q6 allows smaller input transistors Q1 and Q7 and current source Q3 to be used, increasing the integration level and gate speed via decreased capacitance.

Claims47

Dependent claims

A member of a family of logic gates, each of which is for performing a logic operation upon one two-state input to produce a two-state output, said member comprising:

a first input field-effect transistor, operable in an enhancement mode and having gate, drain, and source terminals, said gate terminal being for receiving the two-state input;
and
a control field-effect transistor, operable in an enhancement mode and having gate, drain, and source terminals, said gate terminal of said control transistor being coupled to said source terminal of said first input transistor, said drain terminal of said control transistor being coupled to said drain terminal of said first input transistor, said first input transistor and said control transistor cooperatively performing the logic operation to produce the two-state output at said drain terminal of said control transistor.

A gate, from a family of gates, for performing a logic operation upon a two-state input to-produce a two-state output, said gate comprising:

a first input field-effect transistor, operable in an enhancement mode and having gate, drain, and source terminals, said gate terminal being for receiving said two-state input;
a first source field-effect transistor, operable as a current source and having gate, drain, and source terminals, said source terminal of said first source transistor being coupled to said drain terminal of said first input transistor;
and
a second source field-effect transistor, operable as a current source and having gate, drain, and source terminals, said drain terminal of said second source transistor being coupled to said source terminal of said first input transistor, said first input transistor and said first and second source transistors cooperatively partially performing the logic operation upon the two-state input.

1 more element

A logic gate, for producing a digital output in response to first and second digital inputs, comprising:

a first input field-effect transistor, operable in an enhancement mode and having gate, drain, and source terminals, said gate terminal being for receiving the first digital input;
a second input field-effect transistor, operable in an enhancement mode and having gate, drain, and source terminals, said gate terminal being for receiving the second digital input, said drain and source terminals of said first input transistor being coupled to said drain and source terminals, respectively, of said second input transistor;
and
a control field-effect transistor, operable in an enhancement mode and having gate, drain, and source terminals, said gate terminal of said control transistor being coupled to said source terminal of said first input transistor, said drain terminals of said control transistor and said first and second input transistors being coupled together, said control transistor and said first and second input transistors cooperatively responding to the first and second digital inputs to produce the digital output.

1 more element

A logic gate, for producing a digital output in response to a first digital input, comprising:

a first input field-effect transistor, operable in an enhancement mode and having gate, drain, and source terminals;
and,
a control field-effect transistor, operable in an enhancement mode and having gate, drain, and source terminals, said gate terminal of said control transistor being coupled to said source terminal of said first input transistor, said drain terminal of said control transistor being coupled to said drain terminal of said first input transistor.

Dependencies are inferred from the claim text.

FFL/QFL FET logic circuits

Life of this patent

FFL/QFL FET logic circuits

Life of this patent

Abstract

Claims47