Process of fabricating a heterojunction field effect transistor

A process of fabricating a heterojunction field effect transistor, comprising the steps of:

• a) preparing a semi-insulating substrate having a major surface;
• b) removing a portion of said semi-insulating substrate to form a side wall substantially perpendicular to said major surface;
• c) growing a first layer of a first compound semiconductor material on said semi-insulating substrate;
• d) growing a second layer of a second compound semiconductor material on said first layer, said second compound semiconductor material containing at least first and second elements the former of which is obliquely supplied to said second layer with respect to said major surface and the latter of which is perpendicularly supplied to the second layer with respect to the major surface, said second layer having a portion over said side wall different in composition than the remaining portion of said second layer;
• e) growing a third layer of a third compound semiconductor material on said second layer;
• f) removing a part of said third layer to expose a part of said second layer;
• g) forming electrodes, one of which is formed on the part of said second layer and the others of which are provided on said third layer.