US 5,025,366 AGranted

Organization of an integrated cache unit for flexible usage in cache system design

AssigneeAdvanced Micro Devices, Inc.

InventorGigy Baror

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Abstract

Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance with an alternative embodiment of the invention, the cache memory may be externally located. Flexible cache system design is achieved by the specification of desired cache features through the setting of appropriate cache option bits. The disclosed methods and apparatus support this user oriented approach to flexible system design. The actual setting of option bits may be performed under software control and allows a high performance cache system to be designed with few parts, at low cost and with the ability to perform with high efficiency.

Claims38

Dependent claims

A computer system comprising a programmable cache unit on a single integrated circuit chip, at least one central processing unit (CPU), a memory separate from the cache unit, a memory bus for coupling addresses and data between the CPU and said memory, a memory bus interface unit connected between the memory bus and the cache unit for controlling coupling of addresses and data between the cache unit and the memory bus, an address bus coupled to the CPU, a data bus coupled to the CPU, a processor bus interface unit connected between the address and data buses and the cache unit for controlling coupling of data between the data bus and the cache unit, said cache unit including:

(a) memory array means, tag array means and valid array means, said programmable cache unit being coupled to said processor bus interface unit and said memory bus interface unit performing cache functions, an address bus in the cache unit connected to the processor bus interface unit connecting the memory array means of the programmable cache unit with said tag array means and valid array means so that said tag array means and valid array means control coupling of signals between the processor and the memory array means of the programmable cache unit via the processor bus interface unit;
said tag array means, said valid array means and said memory array means being organized as a 2.sup.n way set associative cache, where n is an integer greater than or equal to zero;
and
(b) means for controlling said programmable cache unit so said memory means separate from said programmable cache unit is coupled with said tag array means and valid array means to be responsive to signals derived from said tag array means and valid array means so that said tag array means and valid array means control coupling of signals between the CPU and the memory means separate from said programmable cache unit.

1 more element

A method of operating a programmable cache unit including tag array means, valid array means and memory array means, said tag array means, said valid array means and said memory array means being organized as a 2.sup.n way set associative cache, where n is an integer greater than or equal to zero, the cache unit performing cache functions in a computing system, the computer system including:

the cache unit, at least one central processing unit ("CPU"), a memory means separate from the cache unit, processor bus means providing communication between said CPU and the cache unit, a cache unit/processor means interface, memory bus means providing communication between said memory means and the cache unit, and a cache unit/memory bus interface;
comprising the steps of:
(a) activating said cache unit to control the cache unit/processor bus means interface via a processor bus unit of said processor bus means;
(b) activating said cache unit to control the cache unit/memory bus interface via a memory bus unit of said memory bus means;
(c) activating said cache unit from within said cache unit to perform cache functions the cache unit being activated to perform the cache functions by coupling the memory array means, tag array means and valid array means with said CPU via said processor bus unit and said memory bus unit;
and
(c) coupling said memory means separate from the cache unit with said tag array means and valid array means so said memory means separate from the cache unit is coupled with said CPU in response to signals derived from said tag array manes and said valid array means.

4 more elements

Dependencies are inferred from the claim text.