Superconducting-semiconducting circuits, devices and systems
AssigneeMicroelectronics and Computer Technology Corporation
InventorsHarry Kroger, Uttam S. Ghoshal
Life of this patent
Estimating the term…
Abstract
A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions as a nearly ideal pass gate in cryogenic applications.
Claims20
A superconducting-semiconducting electrical circuit element comprising:
- (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions;
- and
- (b) a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from said superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from said superconducting device.
A superconducting-semiconducting electrical circuit element comprising:
- (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions;
- and
- (b) a voltage transducer adapted to receive as an input signal a signal formed in the output stage of said superconducting charge controlled device, and for providing a semiconductor switching level voltage output signal in response to changes in state of the output signal from said superconducting charge controlled device.
A digital selector network formed of a plurality of superconducting-semiconducting electrical circuit elements, each of said elements comprising:
- (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions;
- and
- (b) a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from said superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from said superconducting device.
A digital barrel shifter circuit of the type adapted to permit the rotation or shifting of the contents of data present on a plurality of bus lines B.sub.i into data lines D.sub.i under control of a plurality of control signals S.sub.i, said shifter circuit being comprised of a plurality of superconductor-semiconductor electrical circuit elements, each of said circuit elements comprising:
- (a) a superconducting charge controlled three-terminal device, having a device control terminal, a second terminal and a third terminal, wherein the output current between the second and third terminals is controlled by the voltage applied to the control terminal, and wherein the output current exhibits superconducting characteristics as a function of temperature and input charge conditions;
- and
- (b) a cryogenic semiconducting interconnect circuit, adapted to receive as an input an output signal from said superconducting device, and to provide a semiconductor switching voltage level output signal modulated by the input signal from said superconducting device;
- and
- (c) wherein said control terminals of said circuit elements are selectively coupled to said control signals S.sub.i, said second terminals of said circuit elements are selectively coupled to said bus lines B.sub.i, and said third terminals of said circuit elements are selectively coupled to said data lines D.sub.i.
Dependencies are inferred from the claim text.