Method of making ferroelectric memory devices
AssigneeRamtron Corporation
InventorsGeorge A. Rohrer, Larry D. McMillin
Life of this patent
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Abstract
A monolithic semiconductor integrated circuit-ferroelectric device is disclosed together with the method of manufacturing same. The ferroelectric device preferably consists of a layer of stable ferroelectric potassium nitrate disposed between electrical contacts positioned on opposite surfaces of the ferroelectric layer. The ferroelectric layer has a thickness of less than 110 microns, and preferably falling within a range of from 100 Angstrom units to 25,000 Angstrom units. The process of manufacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.
Claims24
A method of fabricating a monolithic ferroelectric memory device coupled to an integrated circuit comprising the steps of:
- forming first layer interconnects coupled to the integrated circuit;
- depositing a non-semiconductor dielectric and forming interconnect and bonding pad vias therein;
- depositing a conductive layer and forming a bottom electrode;
- applying a ferroelectric layer;
- depositing a conductive layer and forming a top electrode;
- and
- applying conductive material to the bonding and interconnect pads.
A method of fabricating a monolithic ferroelectric memory device coupled to an integrated circuit comprising the steps of:
- forming first layer interconnects coupled to the integrated circuit;
- depositing a non-semiconductor dielectric and establishing interconnect and bond pad vias therein;
- depositing a conductive layer and forming a bottom electrode;
- depositing a second non-semiconductor dielectric and forming vias therein;
- depositing a conductive layer and forming a top electrode;
- and
- applying conductive material to the bonding and interconnect pads.
A method of fabricating a monolithic ferroelectric memory device coupled to an integrated circuit comprising the steps of:
- forming first layer interconnects coupled to the integrated circuit;
- depositing a non-semiconductor dielectric and establishing interconnect and bonding pad vias therein;
- depositing a conductive layer and forming a bottom electrode;
- depositing a second non-conductive dielectric and forming vias therein;
- applying a ferroelectric layer;
- depositing a conductive layer and forming a top electrode;
- depositing a top non-semiconductor dielectric layer uniformly;
- removing said top non-semiconductor dielectric layer from the bonding and interconnect pads;
- and
- applying conductive material to the bonding and interconnect pads.
Dependencies are inferred from the claim text.