US 5,023,838 A · Random access memory device with integral logic capability

Abstract

A random access memory (RAM) device capable of performing logic combinations of new and previously stored data in a single memory access cycle. In contrast to conventional RAM data combination sequences, which involve a succession of read-modify-write cycles, the present architecture implements logical combinations of new RAM data with old RAM data during a single access cycle. In a preferred arrangement, decoding logic combines the new data with mode select signals to generate a set of FORCE 1, FORCE 0, COMP and NOOP control signals. The control signals regulate the bit line sense amplifier and logic to allow direct interaction with the bit line data during RAM addressing. The invention is particularly useful in graphic video display systems frame buffers where rapid pattern changes are difficult to implement using moderate speed and cost RAM devices.

Claims3

Dependent claims

A circuit for rapidly entering logic combinations of new and previously stored data into a random access memory, comprising:

a random access memory having a row decoder for selecting an addressed row line from the array;
sense amplifier responsive to data signals from the memory array bit lines;
mode logic means for generating control signals as defined by selected logical combinations and new data signals;
and
means for altering the data in the sense amplifier during the addressing of a row line from the array in response to mode logic control signals
wherein the sense amplifier and means for directly altering the data in the sense amplifier are situated between the random access memory array bit lines and a column decoder;
and
wherein the means for altering the data in the sense amplifier includes:
means for producing a direct complement of the previously stored data selected during the addressing of a row line;
means for sensing the binary state of the memory array bit lines;
and
means for selectively driving the binary state of the sensed memory array bit line states to a binary "0" or binary "1" as defined by the mode logic control signals.

9 more elements

Dependencies are inferred from the claim text.

Random access memory device with integral logic capability

Life of this patent

Random access memory device with integral logic capability

Life of this patent

Abstract

Claims3