Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines
AssigneeXerox Corporation
InventorWilliam F. Gunning
Life of this patent
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Abstract
This invention provides very wide channel, open drain, N-channel CMOS drivers and cascode CMOS receivers for interfacing VLSI CMOS circuits to transmission lines which are terminated by their characteristic resistive impedances to voltage levels on the order of about 1.2 v-2.0 v. These GTL (a coined descriptor) drivers and receivers typically operate with a voltage swing on the order of about 0.8 v-1.4 v on such transmission lines for carrying out binary communications between CMOS circuits configured to operate with standard 5 v rail-to-rail voltage swings for their internal signals.
Claims5
An interface for interfacing VLSI CMOS binary circuits to a terminated transmission line for binary communications between said circuits at signal levels providing a signal swing of about 0.8 v-1.4 v between a line terminating voltage level of about 1.2 v-2.0 v and a low voltage level of about 0.4 v-0.6 v;
- said interface comprising
- driver means for feeding binary signals from said CMOS circuits to said transmission line;
- each of said driver means including an N-channel transistor means having a drain coupled to said transmission line, a source returned to ground, and a gate coupled to receive binary signals from one of said CMOS circuits;
- the gate of said transistor means being of predetermined effective width and length, with its width being plural orders of magnitude greater than its length.
An interface for interfacing VLSI CMOS binary circuits to a terminated transmission line for binary communications between said circuits at signal levels providing a nominal signal swing of up to about 1.4 v between a line terminating voltage level of up to about 2.0 v and a lower voltage level;
- said interface comprising
- driver means for feeding binary signals from said CMOS circuits to said transmission line;
- each of said driver means including an N-channel transistor means having a drain coupled to said transmission line, a source returned to ground, and a gate coupled to receive binary signals from one of said CMOS circuits;
- the gate of said transistor means being of predetermined effective width and length, with its width being plural orders of magnitude greater than its length.
Dependencies are inferred from the claim text.