# US 5,023,205 A · Method of fabricating hybrid circuit structures

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- Number: US 5,023,205 A
- Document ID: US5023205A
- Status: Granted
- Kind: A
- Application number: 07/344,252
- Filed: 1989-04-27
- Granted: 1991-06-11
- Earliest claimed: 1989-04-27
- Assignees: Polycon Corporation
- Inventors: John J. Reche
- Web page: https://patentgrep.com/patent/US5023205A

## CPC

- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H05K 3/328: by welding
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- Y10S 148/02: Contacts, special
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Hybrid circuit structures and methods of fabrication which result in improved manufacturing yields and reliability in use are disclosed. The methods disclosed include methods of forming on the hybrid circuit substrate, a ground plane, bonding pads, and interconnects, which minimize the likelihood of forming catastrophic defects in various insulation layers during the manufacturing processing, which minimize the likelihood of damage to the bonding pads when bonding integrated circuit leads thereto, and which minimize the thermal stressing of a finished product due to the differential expansion between the various layers making up the same. Alternate methods and structures are disclosed.

## Claims

### Claim 1

In a method of forming a ground plane on a substrate in a high density multilayer interconnect fabrication process, comprising the steps of;
(a) depositing a layer of metal on the substrate;
(b) putting a layer of polymer over the layer of metal deposited in step (a);
(c) depositing a layer of metal over the layer of polymer in step (b);
(d) patterning the layer of metal of step (c), and the layer of polymer of step (b) where the same is not masked by the remaining parts of the metal layer of step (c);
(e) putting a layer of polymer over the layer of metal deposited in step (a);
(f) depositing a layer of metal over the layer of polymer of step (e);
(g) patterning the layer of metal of step (f);
(h) putting a layer of polymer over the patterned layer of metal;
(i) patterning the layer of polymer of step (h), and the layer of polymer of step (e) where the same is not masked by the metal layer of steps (f) and (g); and whereby the first patterning of the polymer layer of step (e) occurs after the polymer layer of step (h) is applied; and wherein steps (b) through (d) in part form the bonding pads for the high density multilayer interconnect.

### Claim 2 (depends on 1)

The method of claim 1 further comprising the steps of;
(j) depositing a layer of metal over the layer of polymer of steps (h) and (i), and;
(k) patterning the layer of metal of step (j),
whereby the layer of metal of steps (j) and (k) will interconnect the same with the metal layer of steps (b) and (c) in regions where the latter are exposed by the patterning of step (i).

### Claim 3 (depends on 2)

The method of claim 2 wherein step (i) exposes at least one region of the metal layer of steps (f) and (g), whereby the layer of metal of steps (j) and (k) will interconnect the metal layer of steps (f) and (g) and the metal layer of steps (j) and (k).

### Claim 4 (depends on 1)

The method of claim 1 wherein the polymer layer of step (b) is a layer of high compressive yield strength polymer.

### Claim 5 (depends on 4)

The method of claim 4 wherein the polymer layer of step (b) is also a layer of low dielectric constant polymer.

### Claim 6 (depends on 5)

The method of claim 5 wherein the polymer layers other than that of step (b) are layers of low modulus of elasticity polymers.

### Claim 7 (depends on 6)

The method of claim 6 wherein the polymer layer of all steps other than step (b) are made substantially thicker than the polymer layer of step (b).

### Claim 8 (depends on 1)

The method of claim 1 wherein steps (b) through (d) in part form the bonding pads for the high density multilayer interconnect.

### Claim 9 (depends on 8)

The method of claim 8 wherein layers of polymer above the bonding pads are not patterned to expose the bonding pads until no further layers of polymer are to be applied thereover prior to bonding leads thereto.

### Claim 10 (depends on 1)

The method of claim 1 wherein the polymers layers are layers of low modulus of elasticity polymers.