Vernier structure for flip chip bonded devices
AssigneePlessey Overseas Limited
InventorDavid J. Pedder
Life of this patent
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Abstract
A flip-chip solder bonding structure having first and second components. Each component is made from a substrate haivng on one surface an array of solderable pads. Selected pads have solder bumps deposited thereon with each surface having a plurality of alignment marks formed thereon whereby when the components are positioned face to face, the arrays register with one another to enable a solder bond to be formed. The respective pluralities of alignment marks may be inspected to assess their relative positions in order to determine the accuracy of the solder bond. The solderable pads and the alignment marks on each surface are formed during the same processing stage as metallized regions. The solder bumps are applied to the metallized regions forming the alignment marks.
Claims7
A flip-chip solder bonding structure comprising first and second components each comprising a substrate having on one surface an array of solderable pads, selected pads having solder bumps deposited thereon, and each surface having a plurality of alignment marks formed thereon whereby when the components are positioned face to face, the arrays register with one another to enable a solder bond to be formed and the respective pluralities of alignment marks may be inspected to assess their relative positions in order to determine the accuracy of the solder bond, the solderable pads and the alignment marks on each surface being formed during the same processing stage as metallised regions and wherein solder bumps are applied to the metallised regions forming the alignment marks.
Dependencies are inferred from the claim text.